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d a t a sh eet preliminary speci?cation file under integrated circuits, ic22 2000 mar 15 integrated circuits SAA7114h pal/ntsc/secam video decoder with adaptive pal/ntsc comb filter, vbi-data slicer and high performance scaler
2000 mar 15 2 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h contents 1 features 1.1 video decoder 1.2 video scaler 1.3 vertical blanking interval (vbi) data decoder and slicer 1.4 audio clock generation 1.5 digital i/o interfaces 1.6 miscellaneous 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 decoder 8.2 decoder output formatter 8.3 scaler 8.4 vbi-data decoder and capture (subaddresses 40h to 7fh) 8.5 image port output formatter (subaddresses 84h to 87h) 8.6 audio clock generation (subaddresses 30h to 3fh) 9 input/output interfaces and ports 9.1 analog terminals 9.2 audio clock signals 9.3 clock and real-time synchronization signals 9.4 video expansion port (x-port) 9.5 image port (i-port) 9.6 host port for 16-bit extension of video data i/o (h-port) 9.7 basic input and output timing diagrams i-port and x-port 10 boundary scan test 10.1 initialization of boundary scan circuit 10.2 device identification codes 11 limiting values 12 thermal characteristics 13 characteristics 14 application information 15 i 2 c-bus description 15.1 i 2 c-bus format 15.2 i 2 c-bus details 15.3 programming register audio clock generation 15.4 programming register vbi-data slicer 15.5 programming register interfaces and scaler part 16 programming start set-up 16.1 decoder part 16.2 audio clock generation part 16.3 data slicer and data type control part 16.4 scaler and interfaces 17 package outline 18 soldering 18.1 introduction to soldering surface mount packages 18.2 reflow soldering 18.3 wave soldering 18.4 manual soldering 18.5 suitability of surface mount ic packages for wave and reflow soldering methods 19 definitions 20 life support applications 21 purchase of philips i 2 c components
2000 mar 15 3 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 1 features 1.1 video decoder six analog inputs, internal analog source selectors, e.g. 6 cvbs or (2 y/c and 2 cvbs) or (1 y/c and 4 cvbs) two analog preprocessing channels in differential cmos style inclusive built-in analog anti-alias filters fully programmable static gain or automatic gain control (agc) for the selected cvbs or y/c channel automatic clamp control (acc) for cvbs, y and c switchable white peak control two 9-bit video cmos analog-to-digital converters (adcs), digitized cvbs or y/c signals are available on the expansion port on-chip line-locked clock generation according itu 601 digital pll for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade vtr requires only one crystal (32.11 or 24.576 mhz) for all standards horizontal and vertical sync detection automatic detection of 50 and 60 hz field frequency, and automatic switching between pal and ntsc standards luminance and chrominance signal processing for pal bgdhin, combination pal n, pal m, ntsc m, ntsc-japan, ntsc 4.43 and secam adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation C increased luminance and chrominance bandwidth for all pal and ntsc standards C reduced cross colour and cross luminance artefacts pal delay line for correcting pal phase errors independent brightness contrast saturation (bcs) adjustment for decoder part user programmable sharpness control independent gain and offset adjustment for raw data path. 1.2 video scaler horizontal and vertical down-scaling and up-scaling to randomly sized windows horizontal and vertical scaling range: variable zoom to 1 64 (icon); it should be noted that the h and v zoom are restricted by the transfer data rates anti-alias and accumulating filter for horizontal scaling vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy) horizontal phase correct up and down scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width) two independent programming sets for scaler part, to define two ranges per field or sequences over frames fieldwise switching between decoder part and expansion port (x-port) input brightness, contrast and saturation controls for scaled outputs. 1.3 vertical blanking interval (vbi) data decoder and slicer versatile vbi-data decoder, slicer, clock regeneration and byte synchronization e.g. for world standard teletext (wst), north-american broadcast text system (nabts), close caption, wide screen signalling (wss) etc. 1.4 audio clock generation generation of a field locked audio master clock to support a constant number of audio clocks per video field generation of an audio serial and left/right (channel) clock signal.
2000 mar 15 4 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 1.5 digital i/o interfaces real-time signal port (r port), inclusive continuous line-locked reference clock and real-time status information supporting rtc level 3.1 (refer to external document rtc functional specification for details) bi-directional expansion port (x-port) with half duplex functionality (d1), 8-bit yuv C output from decoder part, real-time and unscaled C input to scaler part, e.g. video from mpeg decoder (extension to 16-bit possible) video image port (i-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals discontinuous data streams supported 32-word 4-byte fifo register for video output data 28-word 4-byte fifo register for decoded vbi output data scaled 4:2:2, 4:1:1, 4:2:0, 4:1:0 yuv output scaled 8-bit luminance only and raw cvbs data output sliced, decoded vbi-data output. 1.6 miscellaneous power-on control 5 v tolerant digital inputs and i/o ports software controlled power saving standby modes supported programming via serial i 2 c-bus, full read-back ability by an external controller, bit rate up to 400 kbits/s boundary scan test circuit complies with the ieee std. 1149.b1 - 1994 . 2 applications desktop video multimedia digital television image processing video phone applications. 3 general description the SAA7114h is a video capture device for applications at the image port of vga controllers. the SAA7114h is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and adc, an automatic clamp and gain control, a clock generation circuit (cgc), a digital multi-standard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit. it is a highly integrated circuit for desktop video applications. the decoder is based on the principle of line-locked clock decoding and is able to decode the colour of pal, secam and ntsc signals into itu 601 compatible colour component values. the SAA7114h accepts as analog inputs cvbs or s-video (y/c) from tv or vcr sources, including weak and distorted signals. an expansion port (x-port) for digital video (bi-directional half duplex, d1 compatible) is also supported to connect to mpeg or video phone codec. at the so called image port (i-port) the SAA7114h supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to vga controllers. the target application for SAA7114h is to capture and scale video images, to be provided as digital video stream through the image port of a vga controller, for display via vgas frame buffer, or for capture to system memory. in parallel SAA7114h incorporates also provisions for capturing the serially coded data in the vertical blanking interval (vbi-data). two principal functions are available: 1. to capture raw video samples, after interpolation to the required output data rate, via the scaler 2. a versatile data slicer (data recovery) unit. SAA7114h incorporates also a field locked audio clock generation. this function ensures that there is always the same number of audio samples associated with a field, or a set of fields. this prevents the loss of synchronization between video and audio, during capture or playback. the circuit is i 2 c-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s).
2000 mar 15 5 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 4 quick reference data note 1. power dissipation is measured in cvbs input mode (only one adc active) and 8-bit image port output mode, expansion port is 3-stated. 5 ordering information symbol parameter min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v v dddc digital core supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.1 3.3 3.5 v t amb operating ambient temperature 0 - 70 c p a+d analog and digital power dissipation; note 1 - 0.45 - w type number package name description version SAA7114h lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1
2000 mar 15 6 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 6 block diagram u ll pagewidth mhb528 fir-prefilter prescaler and scaler bcs general purpose vbi-data slicer video/text arbiter text fifo video fifo programming register array a/b register mux event controller image port pin mapping x port i/o formatting expansion port pin mapping i/o control i 2 c-bus real-time output llc 13 ai2d line fifo buffer vertical scaling horizontal fine (phase) scaling 32 to 8(16) mux 47 itri 21 agnd 19 ai1d 22 aout 10 ai24 12 ai23 14 ai22 16 ai21 18 ai12 20 ai11 6 xtalo 7 xtali 4 xtout 27 ce 30 28 97 tck 98 tms 99 tdi 3 v dd(xtal) 8 v ss(xtal) 5 v ddd(ico1) to v ddd(ico6) 33, 43, 58, 68, 83, 93 v ddd(ep1) to v ddd(ep4) 1, 25, 51, 75 v dda0 to v dda2 23, 17, 11 v ssd(ico1) to v ssd(ico3) 38, 63, 88 v ssd(ep1) to v ssd(ep4) 26, 50, 76, 100 v ssa0 to v ssa2 24, 15, 9 amxclk 41 tdo 2 amclk 37 alrclk 40 asclk 39 llc2 29 rtco 36 rts0 34 rts1 35 xclk 94 xdq 95 81, 82, 84 to 87 89, 90 xrh 92 xrv 91 xrdy 96 sda 32 scl 31 test5 79 test4 78 test3 77 test2 74 test1 73 test0 44 64 to 67, 69 to 72 xtri 80 chrominance of 16-bit input boundary scan test clock generation and power-on control analog dual adc digital decoder with adaptive comb filter audio clock generation 42 itrdy 45 iclk 49 igp1 48 igp0 52 igpv 53 igph 46 idq 54 to 57, 59 to 62 ipd [ 7:0 ] hpd [ 7:0 ] xpd [ 7:0 ] res SAA7114h trst (1) (1) fig.1 block diagram. (1) the pins rtco and alrclk are used for configuration of the i 2 c-bus interface and the definition of the crystal oscillator frequency at reset (pin strapping).
2000 mar 15 7 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 7 pinning symbol pin type description v ddd(ep1) 1 p external digital pad supply voltage 1 (+3.3 v) tdo 2 o test data output for boundary scan test; note 1 tdi 3 i test data input for boundary scan test; note 1 xtout 4 o crystal oscillator output signal; auxiliary signal v ss(xtal) 5 p ground for crystal oscillator xtalo 6 o 24.576 mhz (32.11 mhz) crystal oscillator output; not connected if ttl clock input of xtali is used xtali 7 i input terminal for 24.576 mhz (32.11 mhz) crystal oscillator or connection of external oscillator with ttl compatible square wave clock signal v dd(xtal) 8 p supply voltage for crystal oscillator v ssa2 9 p ground for analog inputs ai2n ai24 10 i analog input 24 v dda2 11 p analog supply voltage for analog inputs ai2n (+3.3 v) ai23 12 i analog input 23 ai2d 13 i differential input for adc channel 2 (pins ai24, ai23, ai22 and ai21) ai22 14 i analog input 22 v ssa1 15 p ground for analog inputs ai1n ai21 16 i analog input 21 v dda1 17 p analog supply voltage for analog inputs ai1n (+3.3 v) ai12 18 i analog input 12 ai1d 19 i differential input for adc channel 1 (pins ai12 and ai11) ai11 20 i analog input 11 agnd 21 p analog ground connection aout 22 o do not connect; analog test output v dda0 23 p analog supply voltage (+3.3 v) for internal clock generation circuit (cgc) v ssa0 24 p ground for internal clock generation circuit v ddd(ep2) 25 p external digital pad supply voltage 2 (+3.3 v) v ssd(ep1) 26 p external digital pad supply ground 1 ce 27 i chip enable or reset input (with internal pull-up) llc 28 o line-locked system clock output (27 mhz nominal) llc2 29 o line-locked 1 2 clock output (13.5 mhz nominal) res 30 o reset output (active low) scl 31 i(/o) serial clock input (i 2 c-bus) with inactive output path sda 32 i/o serial data input/output (i 2 c-bus) v ddd(ico1) 33 p internal digital core supply voltage 1 (+3.3 v) rts0 34 o real-time status or sync information, controlled by subaddresses 11h and 12h; see section 15.2.18, 15.2.19 and 15.2.20 rts1 35 o
2000 mar 15 8 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h rtco 36 (i/)o real-time control output; contains information about actual system clock frequency, ?eld rate, odd/even sequence, decoder status, subcarrier frequency and phase and pal sequence (see external document rtc functional description , available on request); the rtco pin is enabled via i 2 c-bus bit rtce; see notes 2, 3 and table 34 amclk 37 o audio master clock output, up to 50% of crystal clock v ssd(ico1) 38 p internal digital core supply ground 1 asclk 39 o audio serial clock output alrclk 40 (i/)o audio left/right clock output; can be strapped to supply via a 3.3 k w resistor to indicate that the default 24.576 mhz crystal (alrclk = 0; internal pull-down) has been replaced by a 32.110 mhz crystal (alrclk = 1); see notes 2 and 4 amxclk 41 i audio master external clock input itrdy 42 i target ready input, image port (with internal pull-up) v ddd(ico2) 43 p internal digital core supply voltage 2 (+3.3 v) test0 44 o do not connect; reserved for future extensions and for testing: scan output iclk 45 i/o clock output signal for image port, or optional asynchronous back-end clock input idq 46 o output data quali?er for image port (optional: gated clock output) itri 47 i(/o) image port output control signal, effects all input port pins inclusive iclk, enable and active polarity is under software control (bits ipe in subaddress 87h); output path used for testing: scan output igp0 48 o general purpose output signal 0; image port (controlled by subaddresses 84h and 85h) igp1 49 o general purpose output signal 1; image port (controlled by subaddresses 84h and 85h) v ssd(ep2) 50 p external digital pad supply ground 2 v ddd(ep3) 51 p external digital pad supply voltage 3 (+3.3 v) igpv 52 o multi purpose vertical reference output signal; image port (controlled by subaddresses 84h and 85h) igph 53 o multi purpose horizontal reference output signal; image port (controlled by subaddresses 84h and 85h) ipd7 to ipd4 54 to 57 o image port data outputs v ddd(ico3) 58 p internal digital core supply voltage 3 (+3.3 v) ipd3 to ipd0 59 to 62 o image port data output v ssd(ico2) 63 p internal digital core supply ground 2 hpd7 to hpd4 64 to 67 i/o host port data i/o, carries uv chrominance information in 16-bit video i/o modes v ddd(ico4) 68 p internal digital core supply voltage 4 (+3.3 v) hpd3 to hpd0 69 to 72 i/o host port data i/o, carries uv chrominance information in 16-bit video i/o modes test1 73 i do not connect; reserved for future extensions and for testing: scan input test2 74 i do not connect; reserved for future extensions and for testing: scan input v ddd(ep4) 75 p external digital pad supply voltage 4 (+3.3 v) v ssd(ep3) 76 p external digital pad supply ground 3 test3 77 i do not connect; reserved for future extensions and for testing: scan input symbol pin type description
2000 mar 15 9 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h notes 1. in accordance with the ieee1149.1 standard the pads tdi, tms, tck and trst are input pads with an internal pull-up transistor and tdo is a 3-state output pad. 2. pin strapping is done by connecting the pin to supply via a 3.3 k w resistor. during the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. for the default setting no strapping resistor is necessary (internal pull-down). 3. pin rtco: operates as i 2 c-bus slave address pin; rtco = 0 slave address 42h/43h (default); rtco = 1 slave address 40h/41h. 4. pin alrclk: 0 = 24.576 mhz crystal (default); 1 = 32.110 mhz crystal. 5. for board design without boundary scan implementation connect the trst pin to ground. 6. this pin provides easy initialization of the boundary scan test (bst) circuit. trst can be used to force the test access port (tap) controller to the test_logic_reset state (normal operation) at once. test4 78 o do not connect; reserved for future extensions and for testing: scan output test5 79 i do not connect; reserved for future extensions and for testing: scan input xtri 80 i x-port output control signal, affects all x-port pins (xpd7 to xpd0, xrh, xrv, xdq and xclk), enable and active polarity is under software control (bits xpe in subaddress 83h) xpd7 81 i/o expansion port data xpd6 82 i/o expansion port data v ddd(ico5) 83 p internal digital core supply voltage 5 (+3.3 v) xpd5 to xpd2 84 to 87 i/o expansion port data v ssd(ico3) 88 p internal digital core supply ground 3 xpd1 89 i/o expansion port data xpd0 90 i/o expansion port data xrv 91 i/o vertical reference i/o expansion port xrh 92 i/o horizontal reference i/o expansion port v ddd(ico6) 93 p internal digital core supply voltage 6 (+3.3 v) xclk 94 i/o clock i/o expansion port xdq 95 i/o data quali?er i/o expansion port xrdy 96 o task ?ag or ready signal from scaler, controlled by xrqt trst 97 i test reset input (active low), for boundary scan test (with internal pull-up); notes 5 and 6 tck 98 i test clock for boundary scan test; note 1 tms 99 i test mode select input for boundary scan test or scan test; note 1 v ssd(ep4) 100 p external digital pad supply ground 4 symbol pin type description
2000 mar 15 10 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.2 pin configuration. handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 xtri test5 test4 test3 v ssd(ep3) v ddd(ep4) test2 test1 hpd0 hpd1 hpd2 hpd3 v ddd(ico4) hpd4 hpd5 hpd6 hpd7 v ssd(ico2) ipd0 ipd1 ipd2 ipd3 v ddd(ico3) ipd4 ipd5 ipd6 ipd7 igph igpv v ddd(ep3) v ddd(ep1) tdo tdi xtout v ss(xtal) xtalo xtali v dd(xtal) v ssa2 ai24 v dda2 ai23 ai2d ai22 v ssa1 ai21 v dda1 ai12 ai1d ai11 agnd aout v dda0 v ssa0 v ddd(ep2) v ssd(ep4) tms tck xrdy xdq xclk v ddd(ico6) xrh xrv xpd0 xpd1 v ssd(ico3) xpd2 xpd3 xpd4 xpd5 v ddd(ico5) xpd6 xpd7 scl sda v ddd(ico1) rts0 rts1 rtco amclk v ssd(ico1) asclk alrclk amxclk itrdy v ddd(ico2) test0 iclk idq itri igp0 igp1 v ssd(ep2) v ssd(ep1) ce llc llc2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SAA7114h res trst mhb529
2000 mar 15 11 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 1 8-bit/16-bit and alternative pin functional con?gurations pin symbol 8-bit input modes 16-bit input modes (only for i 2 c-bus programming) alternative input functions 8-bit output modes 16-bit output modes (only for i 2 c-bus programming) alternative output functions i/o configuration programming bits 81, 82, 84 to 87, 89, 90 xpd7 to xpd0 d1 data input y data input d1 decoder output xcode[92h[3]] xpe[1:0]83h[1:0] + pin xtri 94 xclk clock input gated clock input decoder clock output xpe[1:0]83h[1:0] + pin xtri xpck[1:0]83h[5:4] xcks[92h[0]] 95 xdq data quali?er input data quali?er output (href and vref gate) xdq[92h[1]] xpe[1:0]83h[1:0] + pin xtri 96 xrdy input ready output active task a/b ?ag xrqt[83h[2]] xpe[1:0]83h[1:0] + pin xtri 92 xrh horizontal reference input decoder horizontal reference output xdh[92h[2]] xpe[1:0]83h[1:0] + pin xtri 91 xrv vertical reference input decoder vertical reference output xdv[1:0]92h[5:4] xpe[1:0]83h[1:0] + pin xtri 80 xtri output enable input xpe[1:0]83h[1:0] 64 to 67, 69 to 72 hpd7 to hpd0 uv data input uv scaler output icode[93h[7]] iswp[1:0]85h[7:6] i8_16[93h[6]] ipe[1:0]87h[1:0] + pin itri
2000 mar 15 12 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 54 to 57, 59 to 62 ipd7 to ipd0 d1 scaler output y scaler output icode[93h[7]] iswp[1:0]85h[7:6] i8_16[93h[6]] ipe[1:0]87h[1:0] + pin itri 45 iclk clock output clock input icks[1:0]80h[1:0] ipe[1:0]87h[1:0] + pin itri 46 idq data quali?er output gated clock output icks[3:2]80h[3:2] idqp[85h[0]] ipe[1:0]87h[1:0] + pin itri 42 itrdy target ready input 53 igph h-gate output extended h-gate, horizontal pulses idh[1:0]84h[1:0] irhp[85h[1]] ipe[1:0]87h[1:0] + pin itri 52 igpv v-gate output v-sync, vertical pulses idv[1:0]84h[3:2] irvp[85h[2]] ipe[1:0]87h[1:0] + pin itri 49 igp1 general purpose idg1[1:0]84h[5:4] ig1p[85h[3]] ipe[1:0]87h[1:0] + pin itri 48 igp0 general purpose idg0[1:0]84h[7:6] ig0p[85h[4]] ipe[1:0]87h[1:0] + pin itri 47 itri output enable input pin symbol 8-bit input modes 16-bit input modes (only for i 2 c-bus programming) alternative input functions 8-bit output modes 16-bit output modes (only for i 2 c-bus programming) alternative output functions i/o configuration programming bits
2000 mar 15 13 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8 functional description 8.1 decoder 8.1.1 a nalog input processing the SAA7114h offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit cmos adc; see fig.6. 8.1.2 a nalog control circuits the anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. the characteristics are shown in fig.3. during the vertical blanking period, gain and clamping control are frozen. fig.3 anti-alias filter. handbook, full pagewidth 6 v (db) - 42 024 68101214 f (mhz) mgd138 - 6 - 12 - 18 - 24 - 30 - 36 0
2000 mar 15 14 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.1.2.1 clamping the clamp control circuit controls the correct clamping of the analog input signals. the coupling capacitor is also used to store and filter the clamping voltage. an internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. the clamping levels for the two adc channels are fixed for luminance (60) and chrominance (128). clamping time in normal use is set with the hcl pulse at the back porch of the video signal. 8.1.2.2 gain control the gain control circuit receives (via the i 2 c-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (agc) as part of the analog input control (aico). the agc (automatic gain control for luminance) is used to amplify a cvbs or y signal to the required signal amplitude, matched to the adcs input voltage range. the agc active time is the sync bottom of the video signal. signal (white) peak control limits the gain at signal overshoots. the flow charts (see figs 7 and 8) show more details of the agc. the influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. fig.4 analog line with clamp (hcl) and gain range (hsy). handbook, halfpage hcl mgl065 hsy analog line blanking tv line 1 60 255 gain clamp fig.5 automatic gain range. handbook, halfpage analog input level controlled adc input level maximum minimum range 9 db 0 db 0 db mhb325 + 3 db - 6 db (1 v (p-p) 18/56 w )
2000 mar 15 15 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... n dbook, full pagewidth mhb530 holdg gafix wpoff gudl0-gudl2 gai20-gai28 gai10-gai18 hlnrs uptcv mode 3 mode 2 mode 1 mode 0 hsy hcl glimb glimt wipa sltca analog control vbsl source switch clamp circuit analog amplifier dac9 anti-alias filter bypass switch adc2 source switch clamp circuit analog amplifier dac9 anti-alias filter bypass switch adc1 vblnk svref cross multiplexer vertical blanking control clamp control gain control anti-alias control mode control fuse [ 1:0 ] fuse [ 1:0 ] aosl [ 1:0 ] agnd 21 cvbs/chr cvbs/lum 99 ad1byp ad2byp 99 99 22 aout 18 19 20 15 9 13 10, 12, 14, 16 17 11 ai2d ai12 ai24 to ai21 ai1d ai11 test selector and buffer v dda1 v ssa2 v dda2 v ssa1 fig.6 analog input processing using the SAA7114h as differential front-end with 9-bit adc.
2000 mar 15 16 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.7 gain flow chart. handbook, full pagewidth analog input amplifier anti-alias filter adc luma/chroma decoder x hsy > 254 > 254 < 1 < 4 > 248 x = 0 x = 1 - 1/llc2 + 1/llc2 - 1/llc2 + / - 0 + 1/f + 1/l gain accumulator (18 bits) actual gain value 9-bit (agv) [ - 3/ + 6 db ] x stop hsy y update fgv mhb531 agv gain value 9-bit 1 0 1 0 10 1 0 1 0 1 0 10 1 0 0 1 1 0 1 0 vblk 1 0 no action 9 9 dac gain holdg x = system variable. y = (iagv - fgvi) > gudl. vblk = vertical blanking pulse. hsy = horizontal sync pulse. agv = actual gain value. fgv = frozen gain value.
2000 mar 15 17 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.8 clamp and gain flow chart. wipe = white peak level (254). sbot = sync bottom level (1). cll = clamp level [60 y (128 c)]. hsy = horizontal sync pulse. hcl = horizontal clamp pulse. handbook, full pagewidth 10 + clamp - clamp no clamp 10 10 01 10 mgc647 fast - gain slow + gain + gain - gain hcl hsy adc sbot wipe cll analog input gain -> <- clamp vblk no blanking active 10
2000 mar 15 18 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 8.1.3 c hrominance and luminance processing n dbook, full pagewidth mhb532 cvbs-in or chr-in code secs huec dcvf quadrature demodulator pal delay line secam recombination phase demodulator amplitude detector burst gate accumulator loop filter low-pass 1 downsampling subcarrier generation 2 fctc acgc cgain [ 6:0 ] idel [ 3:0 ] incs rtco uv- adjustment secam processing f h /2 switch signal adaptive comb filter ccomb ycomb ldel byps lufi [ 3:0 ] cstd [ 2:0 ] ydel [ 2:0 ] low-pass 2 chbw chroma gain control uv interpolation low-pass 3 lubw uv quadrature modulator cdto cstd [ 2:0 ] subcarrier generation 1 chrominance increment dto-reset subcarrier increment generation and divider chrominance increment delay ldel ycomb uv subtractor delay compensation cvbs-in or y-in chr luminance-peaking or low-pass, y-delay adjustment lcbw [ 2:0 ] y y/cvbs dbri [ 7:0 ] dcon [ 7:0 ] dsat [ 7:0 ] rawg [ 7:0 ] rawo [ 7:0 ] colo brightness contrast saturation control raw data gain and offset control ldel ycomb y-out/ cvbs out uv-out href-out set_raw set_vbi set_raw set_vbi set_raw set_vbi set_raw set_vbi uv fig.9 chrominance and luminance processing.
2000 mar 15 19 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.1.3.1 chrominance path the 9-bit cvbs or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). the frequency is dependent on the chosen colour standard. the time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). eight characteristics are programmable via lcwb3 to lcwb0 to achieve the desired bandwidth for the colour difference signals (pal, ntsc) or the 0 and 90 fm signals (secam). the chrominance low-pass 1 characteristic also influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). if the y-comb filter is disabled by ycomb = 0 the filter influences directly the width of the chrominance notch within the luminance path (large chrominance bandwidth means wide chrominance notch resulting to lower luminance bandwidth). the low-pass filtered signals are fed to the adaptive comb filter block. the chrominance components are separated from the luminance via a two line vertical stage (four lines for pal standards) and a decision logic between the filtered and the non-filtered output signals. this block is bypassed for secam signals. the comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by ycomb (subaddress 09h, bit 6) and/or ccomb (subaddress 0eh, bit 0). it is always bypassed during vbi or raw data lines programmable by the lcrn registers (subaddresses 41h to 57h), see section 8.2. the separated uv-components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influence to the luminance path. its characteristic is controlled by chbw (subaddress 10h, bit 3). for the complete transfer characteristic of low-passes 1 and 2 see figs 10 and 11. the secam processing (bypassed for quam standards) contains the following blocks: baseband bell filters to reconstruct the amplitude and phase equalized 0 and 90 fm signals phase demodulator and differentiator (fm-demodulation) de-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (db or dr white carrier values are subtracted from the signal, controlled by the secam switch signal). the succeeding chrominance gain control block amplifies or attenuates the uv-signal according to the required itu 601/656 levels. it is controlled by the output signal from the amplitude detection circuit within the burst processing block. the burst processing block provides the feedback loop of the chrominance pll and contains: burst gate accumulator colour identification and killer comparison nominal/actual burst amplitude (pal/ntsc standards only) loop filter chrominance gain control (pal/ntsc standards only) loop filter chrominance pll (only active for pal/ntsc standards) pal/secam sequence detection, h/2-switch generation. the increment generation circuit produces the discrete time oscillator (dto) increment for both subcarrier generation blocks. it contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). the pal delay line block eliminates crosstalk between the chrominance channels in accordance with the pal standard requirements. for ntsc colour standards the delay line can be used as an additional vertical filter. if desired, it can be switched off by dcvf = 1. it is always disabled during vbi or raw data lines programmable by the lcrn registers (subaddresses 41h to 47h), see section 8.2. the embedded line delay is also used for secam recombination (cross-over switches).
2000 mar 15 20 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb533 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (mhz) (1) (2) (3) (4) (5) (6) (7) (8) fig.10 transfer characteristics of the chrominance low-pass at chbw = 0. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
2000 mar 15 21 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb534 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (mhz) (1) (2) (3) (4) (5) (6) (7) (8) fig.11 transfer characteristics of the chrominance low-pass at chbw = 1. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
2000 mar 15 22 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.1.3.2 luminance path the rejection of the chrominance components within the 9-bit cvbs or y input signal is done by subtracting the re-modulated chrominance signal from the cvbs input. the comb filtered uv-components are interpolated (upsampled) by the low-pass 3 block. its characteristic is controlled by lubw (subaddress 09h, bit 4) to modify the width of the chrominance notch without influence to the chrominance path. the programmable frequency characteristics available in conjunction with the lcbw2 to lcbw0 settings can be seen in figs 12 to 15. note that these frequency curves are only valid for y-comb disabled filter mode (ycomb = 0). in comb filter mode the frequency response is flat. the centre frequency of the notch is automatically adapted to the chosen colour standard. the interpolated uv-samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. this second dto is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for pal and ntsc standards according to the chosen comb filter algorithm. the two modulated signals are finally added to build the re-modulated chrominance signal. the frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. it can be configured as peaking (resolution enhancement) or low-pass block by lufi3 to lufi0 (subaddress 09h, bits 3 to 0). the 16 resulting frequency characteristics can be seen in fig.16. the lufi3 to lufi0 settings can be used as a user programmable sharpness control. the luminance filter block also contains the adjustable y-delay part; programmable by ydel2 to ydel0 (subaddress 11h, bits 2 to 0).
2000 mar 15 23 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb535 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.12 transfer characteristics of the luminance notch filter in 3.58 mhz mode (y-comb filter disabled) at lubw = 0. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
2000 mar 15 24 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb536 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.13 transfer characteristics of the luminance notch filter in 3.58 mhz mode (y-comb filter disabled) at lubw = 1. (1) lcbw[2:0] = 000 (2) lcbw[2:0] = 010 (3) lcbw[2:0] = 100 (4) lcbw[2:0] = 110 (5) lcbw[2:0] = 001 (6) lcbw[2:0] = 011 (7) lcbw[2:0] = 101 (8) lcbw[2:0] = 111
2000 mar 15 25 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb537 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.14 transfer characteristics of the luminance notch filter in 4.43 mhz mode (y-comb filter disabled) at lubw = 0. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
2000 mar 15 26 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb538 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.15 transfer characteristics of the luminance notch filter in 4.43 mhz mode (y-comb filter disabled) at lubw = 1. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
2000 mar 15 27 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb539 - 1 0 1 2 3 4 5 6 7 8 9 v (db) v (db) f (mhz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f (mhz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 (8) (7) (6) (5) (4) (3) (2) (1) (9) (10) (11) (12) (13) (14) (15) (16) - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 fig.16 transfer characteristics of the luminance peaking/low-pass filter (sharpness). (1) lufi[3:0] = 0001. (2) lufi[3:0] = 0010. (3) lufi[3:0] = 0011. (4) lufi[3:0] = 0100. (5) lufi[3:0] = 0101. (6) lufi[3:0] = 0110. (7) lufi[3:0] = 0111. (8) lufi[3:0] = 0000. (9) lufi[3:0] = 1000. (10) lufi[3:0] = 1001. (11) lufi[3:0] = 1010. (12) lufi[3:0] = 1011. (13) lufi[3:0] = 1100. (14) lufi[3:0] = 1101. (15) lufi[3:0] = 1110. (16) lufi[3:0] = 1111.
2000 mar 15 28 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.1.3.3 brightness contrast saturation (bcs) control and decoder output levels the resulting y (cvbs) and uv-signals are fed to the bcs block, which contains the following functions: chrominance saturation control by dsat7 to dsat0 luminance contrast and brightness control by dcon7 to dcon0 and dbri7 to dbri0 raw data (cvbs) gain and offset adjustment by rawg7 to rawg0 and rawo7 to rawo0 limiting yuv or cvbs to the values 1 (minimum) and 254 (maximum) to fulfil itu recommendation 601/656 . fig.17 yuv range for scaler input and x-port output. itu recommendation 601/656 digital levels with default bcs (decoder) settings dcon[7:0] = 44h, dbri[7:0] = 80h and dsat[7:0] = 40h. equations for modification to the yuv levels via bcs control i 2 c-bus bytes dbri, dcon and dsat. luminance: chrominance: it should be noted that the resulting levels are limited to 1 to 254 in accordance with itu recommendation 601/656 . y out int dcon 68 ----------------- y 128 C () dbri + = uv out int dsat 64 --------------- - c r c b , 128 C () 128 + = n dbook, full pagewidth luminance 100% + 255 + 235 + 128 + 16 0 white black u-component + 255 + 240 + 212 + 212 + 128 + 16 + 44 0 blue 100% blue 75% yellow 75% yellow 100% colourless v-component + 255 + 240 + 128 + 16 + 44 0 red 100% red 75% cyan 75% cyan 100% colourless mgc634 a. y output range. b. u output range (c b ). c. v output range (c r ).
2000 mar 15 29 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.18 cvbs (raw data) range for scaler input, data slicer and x-port output. cvbs levels with default settings rawg[7:0] = 64 and rawo[7:0] = 128. equation for modification of the raw data levels via bytes rawg and rawo: it should be noted that the resulting levels are limited to 1 to 254 in accordance with itu recommendation 601/656 . cvbs out int rawg 64 ------------------ cvbs nom 128 C () rawo + = handbook, full pagewidth luminance + 255 + 209 + 71 + 60 1 white sync bottom black shoulder black sync luminance + 255 + 199 + 60 1 white sync bottom black shoulder = black sync mgd700 a. sources containing 7.5 ire black level offset (e.g. ntsc m). b. sources not containing black level offset.
2000 mar 15 30 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.1.4 s ynchronization the prefiltered luminance signal is fed to the synchronization stage. its bandwidth is further reduced to 1 mhz in a low-pass filter. the sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. the resulting output signal is applied to the loop filter to accumulate all phase deviations. internal signals (e.g. hcl and hsy) are generated in accordance with analog front-end requirements. the loop filter signal drives an oscillator to generate the line frequency control signal lfco, see fig.19. the detection of pseudo syncs as part of the macrovision copy protection standard is also done within the synchronization circuit. the result is reported as flag copro within the decoder status byte at subaddress 1fh. 8.1.5 c lock generation circuit the internal cgc generates all clock signals required for the video input processor. the internal signal lfco is a digital-to-analog converted signal provided by the horizontal pll. it is the multiple of the line frequency: 6.75 mhz = 429 f h (50 hz), or 6.75 mhz = 432 f h (60 hz). internally the lfco signal is multiplied by a factor of 2 and 4 in the pll circuit (including phase detector, loop filtering, vco and frequency divider) to obtain the output clock signals. the rectangular output clocks have a 50% duty factor. table 2 decoder clock frequencies clock frequency (mhz) xtalo 24.576 or 32.110 llc 27 llc2 13.5 llc4 (internal) 6.75 llc8 (virtual) 3.375 fig.19 block diagram of the clock generation circuit. handbook, full pagewidth band pass fc = llc/4 zero cross detection phase detection loop filter divider 1/2 divider 1/2 oscillator mhb330 llc2 llc lfco 8.1.6 p ower - on reset and c hip e nable (ce) input a missing clock, insufficient digital or analog v dda0 supply voltages (below 2.7 v) will start the reset sequence; all outputs are forced to 3-state (see fig.20). the indicator output res is low for about 128 llc after the internal reset and can be applied to reset other circuits of the digital tv system. it is possible to force a reset by pulling the chip enable (ce) to ground. after the rising edge of ce and sufficient power supply voltage, the outputs llc, llc2 and sda return from 3-state to active, while the other signals have to be activated via programming.
2000 mar 15 31 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.20 power-on control circuit. poc = power-on control. ce = chip enable input. xtalo = crystal oscillator output. llcint = internal system clock. resint = internal reset. llc = line-locked clock output. res = reset output handbook, full pagewidth mhb331 128 lcc 896 lcc digital delay some ms 20 to 200 m s pll-delay < 1 ms res (internal reset) llc resint llcint xtalo ce poc v dda poc logic analog poc v ddd digital poc delay clock pll ce llc clk0 resint res
2000 mar 15 32 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.2 decoder output formatter the output interface block of the decoder part contains the itu 656 formatter for the expansion port data output xpd7 to xpd0 (for a detailed description see section 9.4.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. it also controls the selection of the reference signals for the rt port (rtco, rts0 and rts1) and the expansion port (xrh, xrv and xdq). the generation of the decoder data type control signals set_raw and set vbi is also done within this block. these signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers lcr2 to lcr24 (see also chapter 15 i 2 c-bus description, subaddresses 41h to 57h). for each lcr value from 2 to 23 the data type can be programmed individually. lcr2 to lcr23 refer to line numbers. the selection in lcr24 values is valid for the rest of the corresponding field. the upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). the relationship between lcr values and line numbers can be adjusted via voff8 to voff0, located in subaddresses 5bh (bit 4) and 5ah (bits 7 to 0) and foff subaddress 5bh (bit d7). the recommended values are voff[8:0] = 03h for 50 hz sources (with foff = 0) and voff[8:0] = 06h for 60 hz sources (with foff = 1), to accommodate line number conventions as used for pal, secam and ntsc standards; see tables 4 to 7. table 3 data formats at decoder output data type number data type decoder output data format 0 teletext eurowst, ccst raw 1 european closed caption raw 2 video programming service (vps) raw 3 wide screen signalling bits raw 4 us teletext (wst) raw 5 us closed caption (line 21) raw 6 video component signal, vbi region yu v4:2:2 7 cvbs data raw 8 teletext raw 9 vitc/ebu time codes (europe) raw 10 vitc/smpte time codes (usa) raw 11 reserved raw 12 us nabts raw 13 moji (japanese) raw 14 japanese format switch (l20/22) raw 15 video component signal, active video region yu v4:2:2
2000 mar 15 33 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 4 relationship of lcr to line numbers in 525 lines/60 hz systems (part 1) vertical line offset, voff[8:0] = 06h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59h[7:0]); foff = 1 (subaddress 5bh[7]) table 5 relationship of lcr to line numbers in 525 lines/60 hz systems (part 2) vertical line offset, voff[8:0] = 06h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59h[7:0]); foff = 1 (subaddress 5bh[7]) table 6 relationship of lcr to line numbers in 625 lines/50 hz systems (part 1) vertical line offset, voff[8:0] = 03h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59h[7:0]); foff = 1 (subaddress 5bh[7]) table 7 relationship of lcr to line numbers in 625 lines/50 hz systems (part 2) vertical line offset, voff[8:0] = 03h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59h[7:0]); foff = 1 (subaddress 5bh[7]) line number (1st ?eld) 521 522 523 524 525 1 2 3 4 5 6 7 8 9 active video equalization pulses serration pulses equalization pulses line number (2nd ?eld) 259 260 261 262 263 264 265 266 267 268 269 270 271 272 active video equalization pulses serration pulses equalization pulses lcr 24 23456789 line number (1st ?eld) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 nominal vbi-lines f1 active video line number (2nd ?eld) 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 nominal vbi-lines f2 active video lcr 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 line number (1st ?eld) 62162262362462512345 active video equalization pulses serration pulses equalization pulses line number (2nd ?eld) 309 310 311 312 313 314 315 316 317 318 active video equalization pulses serration pulses equalization pulses lcr 24 2345 line number (1st ?eld) 678910111213141516171819202122232425 nominal vbi-lines f1 active video line number (2nd ?eld) 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 nominal vbi-lines f2 active video lcr 67891011121314151617181920212223 24
2000 mar 15 34 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.21 vertical timing diagram for 50 hz/625 line systems. (1) the inactive going edge of the v123 signal indicates whether the field is odd or even. if href is active during the falling edge of v123, the field is odd (field 1). if href is inactive during the falling edge of v123, the field is even. the specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. the control signals listed above are available on pins rts0, rts1, xrh and xrv according to the following table: for further information see section 15.2: tables 55, 56 and 57. name rts0 (pin 34) rts1 (pin 35) xrh (pin 92) xrv (pin 91) href xxx f_itu656 --- x v123 xx - x vgate xx - fid xx -- handbook, full pagewidth mhb540 vgate vsto [ 8:0 ] = 134h vsta [ 8:0 ] = 15h (a) 1st field cvbs itu counting single field counting 1 1 2 2 3 3 4 4 5 5 6 6 7 7 ... ... 22 22 625 312 624 311 623 310 622 309 23 23 fid href f_itu656 v123 (1) vgate cvbs itu counting single field counting fid href f_itu656 v123 (1) vsto [ 8:0 ] = 134h vsta [ 8:0 ] = 15h (b) 2nd field 313 313 314 1 315 2 316 3 317 4 318 5 319 6 ... ... 335 22 312 312 311 311 310 310 309 309 336 23
2000 mar 15 35 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.22 vertical timing diagram for 60 hz/525 line systems. (1) the inactive going edge of the v123 signal indicates whether the field is odd or even. if href is active during the falling edge of v123, the field is odd (field 1). if href is inactive during the falling edge of v123, the field is even. the specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. the control signals listed above are available on pins rts0, rts1, xrh and xrv according to the following table: for further information see section 15.2: tables 55, 56 and 57. name rts0 (pin 34) rts1 (pin 35) xrh (pin 92) xrv (pin 91) href x x x - f_itu656 --- x v123 x x - x vgate x x -- fid x x -- handbook, full pagewidth mhb541 vgate vsto [ 8:0 ] = 101h vsta [ 8:0 ] = 011h (a) 1st field cvbs itu counting single field counting 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ... ... 21 21 3 3 2 2 1 1 525 262 22 22 fid href f_itu656 v123 (1) vgate cvbs itu counting single field counting fid href f_itu656 v123 (1) vsto [ 8:0 ] = 101h vsta [ 8:0 ] = 011h (b) 2nd field 266 3 267 4 268 5 269 6 270 7 271 8 272 9 ... ... 284 21 265 2 264 1 263 263 262 262 285 22
2000 mar 15 36 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.23 horizontal timing diagram (50/60 hz). the signals href, hs, cref2 and cref are available on pins rts0 and/or rts1 (see section 15.2.19 tables 55 and 56); their polarity can be inverted via rtp0 and/or rtp1. the signals href and hs are available on pin xrh (see section 15.2.20 table 57). handbook, full pagewidth 108 - 107 107 - 106 mhb542 cvbs input 140 1/llc 5 2/llc expansion port data output 12 2/llc 720 2/llc 144 2/llc 138 2/llc 720 2/llc burst processing delay adc to expansion port: 0 0 2 2/llc 2 2/llc href (60 hz) hs (60 hz) sync clipped 16 2/llc 1 2/llc programming range (step size: 8/llc) programming range (step size: 8/llc) hs (50 hz) href (50 hz) cref cref2 cref cref2
2000 mar 15 37 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.3 scaler the high performance video scaler (hps) is based on the system as implemented in saa7140, but enhanced in some aspects. vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers, and handshake. the internal data flow from block to block is discontinuous dynamically, due to the scaling process itself. the flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks. therefore the entire scaler acts as a pipeline buffer. depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. the access/bandwidth requirements to the vga frame buffer are reduced significantly. the high performance video scaler in SAA7114h has the following major blocks. acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) prescaler, for horizontal down-scaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for cif format brightness, saturation, contrast control for scaled output data line buffer, with asynchronous read and write, to support vertical up-scaling (e.g. for videophone application, converting 240 into 288 lines, yuv 4 : 2 : 2) vertical scaling, with phase accurate linear phase interpolation (lpi) for zoom and down-scale, or phase accurate accumulation mode (acm) for large down-scaling ratios and better alias suppression variable phase delay (vpd), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square (sqr) and rectangular (ccir) pixel sampling output formatter for scaled yuv 4 : 2 : 2, yu v4:1:1 and y only (format also for raw data) fifo, 32-bit wide, with 64 pixel capacity in yuv formats output interface, 8 or 16 (only if extended by h-port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream. the overall h and v zooming (hv_zoom) is restricted by the input/output data rate relations. with a safety margin of 2% for running in and running out, the maximum hv_zoom is equal to: for example: 1. input from decoder: 50 hz, 720 pixel, 288 lines, 16-bit data at 13.5 mhz data rate, 1 cycle per pixel; output: 8-bit data at 27 mhz, 2 cycles per pixel; the maximum hv_zoom is equal to: 2. input from x-port: 60 hz, 720 pixel, 240 lines, 8-bit data at 27 mhz data rate (itu 656), 2 cycles per pixel; output via i + h-port: 16-bit data at 27 mhz clock, 1 cycle per pixel; the maximum hv_zoom is equal to: the video scaler receives its input signal from the video decoder or from the expansion port (x-port). it gets 16-bit yuv 4:2:2 input data at a continuous rate of 13.5 mhz from the decoder. discontinuous data stream can be accepted from the expansion port (x-port), normally 8-bit wide itu 656 like yuv data, accompanied by a pixel qualifier on xdq. the input data stream is sorted into two data paths, one for luminance (or raw samples), and one for time multiplexed chrominance u and v samples. an yuv 4:1:1 input format is converted to 4:2:2forthe horizontal prescaling and vertical filter scaling operation. the scaler operation is defined by two programming pages a and b, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors, and signal source during odd and even fields). each programming page contains control: for signal source selection and formats for task handling and trigger conditions for input and output acquisition window definition for h-prescaler, v-scaler and h-phase scaling. 0.98 t_input_field t_v_blanking C in_pixel in_lines out_cycle_per_pix t_out_clk ------------------------------------------------------------------------------------------------------------------------------- ------ - 0.98 20 ms 24 64 m s C 720 288 2 37 ns -------------------------------------------------------- 1.18 = 0.98 16.666 ms 22 64 m s C 720 240 1 37 ns -------------------------------------------------------------- 2.34 =
2000 mar 15 38 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h raw vbi-data will be handled as specific input format and need an own programming page (= own task). in vbi pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, but the horizontal fine scaling vpd can be activated. upscaling (oversampling, zooming), free of frequency folding, up to factor 3.5 can be achieved, as required by some software data slicing algorithms. these raw samples are transported through the image port as valid data and can be output as y only format. the lines are framed by sav and eav codes. 8.3.1 a cquisition control and task handling ( subaddresses 80h, 90h, 94h to 9fh and c4h to cfh) the acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the x-port. the acquisition window is generated via pixel and line counters at the appropriate places in the data path. from x-port only qualified pixels and lines (= lines with qualified pixel) are counted. the acquisition window parameters are: signal source selection regarding input video stream and formats from the decoder, or from x-port (programming bits scsrc[1:0]91h[5:4] and fsc[2:0]91h[2:0]) remark : the input of raw vbi-data from internal decoder should be controlled via the decoder output formatter and the lcr registers (see section 8.2 decoder output formatter) vertical offset defined in lines of the video source, parameter yo[11:0]99h[3:0]98h[7:0] vertical length defined in lines of the video source, parameter ys[11:0]9bh[11:8]9ah[7:0] vertical length defined in number of target lines, as result of vertical scaling, parameter yd[11:0]9fh[11:8]9eh[7:0] horizontal offset defined in number of pixels of the video source, parameter xo[11:0]95h[3:0]94h[7:0] horizontal length defined in number of pixels of the video source, parameter xs[11:0]97h[3:0]96h[7:0] horizontal destination size, defined in target pixels after fine scaling, parameter xd[11:0]9dh[3:0]9ch[7:0]. the source start offset (xo11 to xo0, yo11 to yo0) opens the acquisition window, and the target size (xd11 to xd0, yd11 to yd0) closes the window, but the window is cut vertically, if there are less output lines than expected. the trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92h. the task handling is controlled by subaddress 90h (see section 8.3.1.2). 8.3.1.1 input ?eld processing the trigger event for the field sequence detection from external signals (x-port) are defined in subaddress 92h. from the x-port the state of the scalers h-reference signal at the time of the v-reference edge is taken as field sequence identifier fid. for example, if the falling edge of the xrv input signal is the reference and the state of xrh input is logic 0 at that time, the detected field id is logic 0. the bits xfdv[92h[7]] and xfdh[92h[6]] are defining the detection event and state of the flag from the x-port. for the default setting of xfdv and xfdh at 00 the state of the h-input at the falling edge of the v-input is taken. the scaler directly gets a corresponding field id information from the SAA7114h decoder path. the fid flag is used to determine, whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits strc[1:0]90h[1:0]). according to itu 656, fid at logic 0 means first field of a frame. to ease the application, the polarities of the detection results on the x-port signals and the internal decoder id can be changed via xfdh. as the v-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. this can be compensated by switching the v-trigger event, as defined by xdv0, to the opposite v-sync edge or by using the vertical scalers phase offsets. the vertical timing of the decoder can be seen in figs 21 and 22. as the h and v reference events inside the itu 656 data stream (from x-port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.
2000 mar 15 39 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 8 processing trigger and start description xdv1 92h[5] xdv0 92h[4] xdh 92h[2] internal decoder : the processing triggers at the falling edge of the v123 pulse (see figs 21 (50 hz) and 22 (60 hz)), and starts earliest with the rising edge of the decoder href at line number: 4/7 (50/60 hz, 1st field), respectively 3/6 (50/60 hz, 2nd field) (decoder count) 0 1 0 2/5 (50/60 hz, 1st field), respectively 2/5 (50/60 hz, 2nd field) (decoder count) 0 0 0 external itu 656 stream : the processing starts earliest with sav at line number 23 (50 hz system), respectively line 20 (60 hz system) (according itu 656 count) 000 8.3.1.2 task handling the task handler controls the switching between the two programming register sets. it is controlled by subaddresses 90h and c0h. a task is enabled via the global control bits tea[80h[4]] and teb[80h[5]]. the handler is then triggered by events, which can be defined for each register set. in case of a programming error the task handling and the complete scaler can be reset to the initial states by the software reset bit swrst[88h[5]] at logic 0. especially if the programming registers, related acquisition window and scale are reprogrammed, while a task is active, a software reset must be done after programming. contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, swrst at logic 0 sets the internal state machines directly to their idle states. the start condition for the handler is defined by bits strc[1:0]90h[1:0] and means: start immediately, wait for next v-sync, next fid at logic 0 or next fid at logic 1. the fid is evaluated, if the vertical and horizontal offsets are reached. with rptsk[90h[2]] at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task. to support field rate reduction, the handler is also enabled to skip fields (bits fskp[2:0]90h[5:3]) before executing the task. a toggle flag is generated (used for the correct output field processing), which changes state at the beginning of a task, every time a task is activated. examples can be seen in section 8.3.1.3. remarks: to activate a task the start condition must be fulfilled and the acquisition window offsets must be reached . for example, in case of start immediately, and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) of upper region, if not, the actual counted h and v position at the end of the upper task is beyond the programmed offsets and the processing will wait for next v. basically the trigger conditions are checked, when a task is activated . it is important to realize, that they are not checked, while a task is inactive. so you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task a strc[2:0] = 2, yo[11:0] = 310 and task b strc[2:0] = 3, yo[11:0] = 310 results in output field rate of 50 3 hz). after power-on or software reset (via swrst[88h[5]]) task b gets priority over task a .
2000 mar 15 40 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.3.1.3 output ?eld processing as reference for the output field processing, two signals are available for the back-end hardware. these signals are the input field id from the scaler source and a toogle flag, which shows, that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. using a single or both tasks and reducing the field or frame rate with the task handling functionality, the toggle information can be used, to reconstruct an interlaced scaled picture at a reduced frame rate. the toggle flag isnt synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly (see section 8.3.3). with ofidc = 0, the scalers input field id is available as output field id on bit d6 of sav and eav, respectively on pin igp0 (igp1), if fid output is selected. when ofidc[90h[6]] = 1, the toggle information is available as output field id on bit d6 of sav and eav, respectively on pin igp0 (igp1), if fid output is selected. additionally the bit d7 of sav and eav can be defined via conlh[90h[7]]. conlh[90h[7]] = 0 (default) sets d7 to logic 1, a logic 1 inverts the sav/eav bit d7. so its possible to mark the output of the both tasks by different sav/eav codes. this bit can also be seen as task flag on the pins igp0 (igp1), if task output is selected.
2000 mar 15 41 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 9 examples for ?eld processing notes 1. single task every field; ofidc = 0; subaddress 90h at 40h; teb[80h[5]] = 0. 2. tasks are used to scale to different output windows, priority on task b after swrst. 3. both tasks at 1 2 frame rate; ofidc = 0; subaddresses 90h at 43h and c0h at 42h. 4. in examples 3 and 4 the association between input fid and tasks can be flipped, dependent on which time the swrst is de-asserte d. 5. task b at 2 3 frame rate constructed from neighbouring motion phases; task a at 1 3 frame rate of equidistant motion phases; ofidc = 1; subaddresses 90h at 41h and c0h at 45h. 6. task a and b at 1 3 frame rate of equidistant motion phases; ofidc = 1; subaddresses 90h at 41h and c0h at 49h. 7. state of prior field. 8. it is assumed that input/output fid = 0 (= upper lines); up = upper lines; lo = lower lines. 9. o = data output; no = no output. subject field sequence frame/field example 1 (1) example 2 (2)(3) example 3 (2)(4)(5) example 4 (2)(4)(6) 1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2 processed by task a a a b a b a b b a b b a b b a b b a state of detected itu 656 fid 0 1 00101010101 0 10 1 01 toggle ?ag 1 0 1 1 1 0 0 1 0 1 1 0 0 0 (7) 111 (7) 00 bit d6 of sav/eav byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0 (7) 111 (7) 00 required sequence conversion at the vertical scaler (8) up up lo lo up up up up lo lo up up lo lo up lo lo up up lo lo lo up up lo up up up lo lo up lo lo lo up up lo up output (9) o o ooooooooooonooonooo
2000 mar 15 42 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.3.2 h orizontal scaling the overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: where, parameter of prescaler xpsc[5:0] = 1 to 63 and parameter of vpd phase interpolation xscy[12:0] = 300 to 8191 (0 to 299 are only theoretical values). for example, 1 3.5 is to split in 1 4 1.14286. the binary factor is processed by the prescaler, the arbitrary non-integer ratios is achieved via the variable phase delay vpd circuitry, called horizontal fine scaling. latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling scheme. prescaler and fine scaler are building the horizontal scaler of the SAA7114h. using the accumulation length function of the prescaler (xacl[5:0]a1h[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be found. 8.3.2.1 horizontal prescaler (subaddresses a0h to a7h and d0h to d7h) the prescaling function consists of an fir anti-alias filter stage and an integer prescaler, which is building an adaptive prescale dependent low-pass filter, to balance sharpness and aliasing effects. the fir prefilter stage implements different low-pass characteristics to reduce alias for down-scales in the range of 1 to 1 2 . a cif optimized filter is build in, which reduces artefacts for cif output formats (to be used in combination with the prescaler set to 1 2 scale). see table 10. the functionality of the prescaler is defined by: an integer prescaling ratio xpsc[5:0]a0h[5:0] (= 1 to 63), which covers the integer down-scale range 1 to 1 63 an averaging sequence length xacl[5:0]a1h[5:0] (= 0 to 63); range 1 to 64 a dc gain renormalization xdcg[2:0]a2h[2:0]; 1 down to 1 128 the bit xc2_1[a2h[3]], which defines the weighting of the incoming pixels during the averaging process C xc2_1 = 0 t 1 + 1...+ 1 +1 C xc2_1 = 1 t 1 + 2...+ 2 +1 the prescaler builds a prescale dependent fir low-pass, with up to (64 + 7) filter taps. the parameter xacl[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1 xpsc[5:0] . the user can therewith decide between signal bandwidth (= sharpness impression) and alias. equation for xpsc[5:0] calculation is: where, the range is 1 to 63 ( value 0 is not allowed!); npix_in = number of input pixel, and npix_out = number of desired output pixel over the complete horizontal scaler. the use of the prescaler results in a xacl[5:0] and xc2_1 dependent gain amplification. the amplification can be calculated according to the equation: dc gain = ((xacl - xc2_1) + 1) (xc2_1 + 1) it is recommended to use sequence lengths and weights, which results in a 2 n dc gain amplification, as these amplitudes can be renormalized by the xdcg[2:0] controlled shifter of the prescaler. the renormalization range of xdcg[2:0] is 1, 1 2 ... down to 1 128 . other amplifications have to be normalized by using the following bcs control circuitry. in these cases the prescaler has to be set to an overall gain 1, e.g. for an accumulation sequence of 1 + 1 + 1 (xacl[5:0] = 2 and xc2_1 = 0), xdcg[2:0] must be set to 010, equals 1 4 and the bcs has to amplify the signal to 4 3 (satn[7:0] and cont[7:0] value = lower integer of 4 3 64). the use of xacl[5:0] is xpsc[5:0] dependent. xacl[5:0] must be 2 xpsc[5:0]. xacl[5:0] can be used to find a compromise between bandwidth (= sharpness) and alias effects. h-scale ratio output pixel input pixel ------------------------------ = h-scale ratio 1 xpsc[5:0] --------------------------- - 1024 xscy[12:0] ------------------------------ - = xpsc[5:0] lower integer of npix_in npix_out ----------------------- = 1 2 n ------
2000 mar 15 43 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h remark : due to bandwidth considerations xpsc[5:0] and xacl[5:0] can be chosen different to the previous mentioned equations or table 11, as the h-phase scaling is able to scale in the range from zooming up by factor 3 to down-scale by a factor of 1024 8191 . figs 26 and 27 show some resulting frequency characteristics of the prescaler. table 11 shows the recommended prescaler programming. other programmings, than documented in table 11, may result in better alias suppression, but the resulting dc gain amplification needs to be compensated by the bcs control, according to the equation: where: 2 xdcg[2:0] 3 dc gain dc gain = (xc2_1 + 1) xacl[5:0] + (1 - xc2_1). for example, if xacl[5:0] = 5, xc2_1 = 1, then dc gain = 10 and the required xdcg[2:0] = 4. the horizontal source acquisition timing and the prescaling ratio is identical for both luminance path and chrominance path, but the fir filter settings can be defined differently in the two channels. fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. figs 24 and 25 show the frequency characteristics of the selectable fir filters. cont[7:0] satn[7:0] lower integer of 2 xdg[2:0] dc gain 64 ---------------------------------- == table 10 fir pre?lter functions pfuv[1:0]a2h[7:6] pfy[1:0]a2h[5:4] luminance filter coefficients chrominance coefficients 00 bypassed bypassed 01 121 121 10 - 1 1 1.75 4.5 1.75 1 - 1 381083 11 12221 12221 handbook, full pagewidth mhb543 v (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f_sig/f_clock (1) (2) (3) - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 fig.24 luminance prefilter characteristic. (1) pfy[1:0] = 01. (2) pfy[1:0] = 10. (3) pfy[1:0] = 11.
2000 mar 15 44 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb544 v (db) 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 f_sig/f_clock (1) (2) (3) - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 fig.25 chrominance prefilter characteristic. (1) pfuv[1:0] = 01. (2) pfuv[1:0] = 10. (3) pfuv[1:0] = 11. handbook, full pagewidth mhb545 v (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 (1) (2) (3) (4) (5) f_sig/f_clock - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 fig.26 examples for prescaler filter characteristics: effect of increasing xacl[5:0]. xc2_1 = 0; zeros at with xacl = (1), (2), (3), (4) or (5) fn 1 xacl 1 + ------------------------ - =
2000 mar 15 45 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.27 examples for prescaler filter characteristics: setting xc2_1 =1. (1) xc2_1 = 0 and xacl[5:0] = 1. (2) xc2_1 = 1 and xacl[5:0] = 2. (3) xc2_1 = 0 and xacl[5:0] = 3. (4) xc2_1 = 1 and xacl[5:0] = 4. (5) xc2_1 = 0 and xacl[5:0] = 7. (6) xc2_1 = 1 and xacl[5:0] = 8. handbook, full pagewidth mhb546 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 v (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f_sig/f_clock (1) (2) (3) (4) (5) (6) 3 db at 0.25 6 db at 0.33
2000 mar 15 46 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 11 xacl[5:0] usage example note 1. resulting fir function. prescale ratio xps [5:0] recommended values fir prefilter pfy[1:0]/ pfuv[1:0] for lower bandwidth requirements for higher bandwidth requirements xacl[5:0] xc2_1 xdcg[2:0] xacl[5:0] xc2_1 xdcg[2:0] 110 0 0 0 0 0 0to2 1 2 2 2 1 2 1 0 1 0 to 2 (1 2 1) 1 4 (1) (1 1) 1 2 (1) 1 3 34 1 3 3 0 2 2 (12221) 1 8 (1) (1 1 1 1) 1 4 (1) 1 4 48 1 4 4 1 3 2 (122222221) 1 16 (1) (12221) 1 8 (1) 1 5 58 1 4 7 0 3 2 (122222221) 1 16 (1) (11111111) 1 8 (1) 1 6 68 1 4 7 0 3 3 (122222221) 1 16 (1) (11111111) 1 8 (1) 1 7 78 1 4 7 0 3 3 (122222221) 1 16 (1) (11111111) 1 8 (1) 1 8 815 0 4 8 1 4 3 (1111111111111111) 1 16 (1) (122222221) 1 16 (1) 1 9 915 0 4 8 1 4 3 (1111111111111111) 1 16 (1) (122222221) 1 16 (1) 1 10 10 16 1 5 8 1 4 3 (12222222222222221) 1 32 (1) (122222221) 1 16 (1) 1 13 13 16 1 5 16 1 5 3 1 15 15 31 0 5 16 1 5 3 1 16 16 32 1 6 16 1 5 3 1 19 19 32 1 6 32 1 6 3 1 31 31 32 1 6 32 1 6 3 1 32 32 63 1 7 32 1 6 3 1 35 35 63 1 7 63 1 7 3
2000 mar 15 47 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.3.2.2 horizontal ?ne scaling (variable phase delay ?lter; subaddresses a8h to afh and d8h to dfh) the horizontal fine scaling (vpd) should operate at scaling ratios between 1 2 and 2 (0.8 and 1.6), but can also be used for direct scale in the range from 1 7.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. in combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal source and application dependent. for the luminance channel a filter structure with 10 taps is implemented, for the chrominance a filter with 4 taps. luminance and chrominance scale increments (xscy[12:0]a9h[4:0]a8h[7:0] and xscc[12:0]adh[4:0]ach[7:0]) are defined independently, but must be set in a 2 : 1 relation in the actual data path implementation. the phase offsets xphy[7:0]aah[7:0] and xphc[7:0]aeh[7:0] can be used to shift the sample phases slightly. xphy[7:0] and xphc[7:0] covers the phase offset range 7.999t to 1 32 t. the phase offsets should also be programmed in a 2 : 1 ratio. the underlying phase controlling dto has a 13-bit resolution. according to the equations and the vpd covers the scale range from 0.125 to zoom 3.5. vpd acts equivalent to a polyphase filter with 64 possible phases. in combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer down-scaled input picture. 8.3.3 v ertical scaling the vertical scaler of the SAA7114h consists of a line fifo buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 1 64 . the vertical scaler is located between the bcs and horizontal fine scaler, so that the bcs can be used to compensate the dc gain amplification of the acm mode (see section 8.3.3.2) as the internal rams are only 8-bit wide. 8.3.3.1 line fifo buffer (subaddresses 91h, b4h and c1h, e4h) the line fifo buffer is a dual ported ram structure for 768 pixels, with asynchronous write and read access. the line buffer can be used for various functions, but not all functions may be available simultaneously. the line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. for zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. for conversion of a 4 : 2 : 0 or 4:1:0 input sampling scheme (mpeg, video phone, video yuv-9) to ccir like sampling scheme 4:2:2, the chrominance line buffer is read twice of four times, before being refilled again by the source. by means of the input acquisition window definition it has to be preserved, that the processing starts with a line containing luminance and chrominance information for 4:2:0 and 4:1:0 input. the bits fsc[2:1]91h[2:1] are defining the distance between the y/c lines. in case of 4 :2:2 and 4 : 1 : 1 fsc2 to fsc1 have to be set to 00. the line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone application (bit ymir[b4h[4]]). in mirror mode only one active prescaled line can be held in the fifo at a time. the line buffer can be utilized as excessive pipeline buffer for discontinuous and variable rate transfer conditions at expansion port or image port. xscy[12:0] 1024 npix_in xpsc ------------------- - 1 npix_out ----------------------- = xscc[12:0] xscy[12:0] 2 ------------------------------ - =
2000 mar 15 48 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.3.3.2 vertical scaler (subaddresses b0h to bfh and e0h to efh) vertical scaling of any ratio from 64 (theoretical zoom) to 1 63 (icon) can be applied. the vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes. called linear interpolation (lpi) and accumulation (acm) mode, controlled by ymode[b4h[0]]. lpi mode : in linear phase interpolation (lpi) mode (ymode = 0) two neighbouring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. this linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. it interpolates between two consecutive input lines only. lpi mode should be applied for scaling ratios around 1 (down to 1 2 ), it must be applied for vertical zooming . acm mode : the vertical accumulation (acm) mode (ymode = 1) represents a vertical averaging window over multiple lines, sliding over the field. this mode also generates phase correct output lines. the averaging window length corresponds to the scaling ration, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. acm can be applied for down-scales only from ratio 1 down to 1 64 . acm results in a scale dependent dc gain amplification , which has to be precorrected by the bcs control of the scaler part. the phase and scale controlling dto calculates in 16-bit resolution, controlled by parameters yscy[15:0]b1h[7:0]b0h[7:0] and yscc[15:0]b3h[7:0]b2h[7:0], continuously over the entire filed. a start offset can be applied to the phase processing by means of the parameters ypy3[7:0] to ypy0[7:0] in bfh[7:0] to bch[7:0] and ypc3[7:0] to ypc0[7:0] in bbh[7:0] to b8h[7:0]. the start phase covers the range of 255 32 to 1 32 lines offset. by programming appropriate, opposite, vertical start phase values (subaddresses b8h to bfh and e8h to efh) depending on odd/even field id of the source video stream and a/b-page cycle, frame id conversion and field rate conversion are supported (i.e. de-interlacing, re-interlacing). figs 28 and 29 and tables 12 and 13 are describing the use of the offsets. remark: the vertical start phase, as well as scaling ratio are defined independently for luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4:2:2 output processing. the vertical processing communicates on its input side with the line fifo buffer. the scale related equations are: scaling increment calculation for acm and lpi mode, down-scale and zoom: bcs value to compensate dc gain in acm mode (contrast and saturation have to be set): cont[7:0]a5h[7:0] respectively satn[7:0]a6h[7:0] , or 8.3.3.3 use of the vertical phase offsets as shown in section 8.3.1.3, the scaler processing may run randomly over the interlaced input sequence. additionally the interpretation and timing between itu 656 field id and real-time detection by means of the state of h-sync at falling edge of v-sync may result in different field id interpretation. also a vertically scaled interlaced output gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regarding the actual scale at the starting point of operation (see fig.28). four events are to be considered, they are illustrated in fig.29. yscy(c)[15:0] lower integer of 1024 nline_in nline_out ------------------------ - ? ?? = lower integer of nline_out nline_in ------------------------ - 64 ? ?? = lower integer of 1024 yscy[15:0] ------------------------------ - 64 ? ?? =
2000 mar 15 49 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.28 basic problem of interlaced vertical scaling (example: down-scale 3 5 ). handbook, full pagewidth mhb547 mismatched vertical line distances scale dependent start offset correct scale dependent position unscaled input scaled output, no phase offset scaled output, with phase offset ?ld 1 ?ld 2 ?ld 1 ?ld 2 ?ld 1 ?ld 2 fig.29 derivation of the phase related equations (example: interlace vertical scaling down to 3 5 , with field conversion). offset 1024 32 ------------ - 32 1 line shift === a 1 2 -- - input line shift 16 == d = no offset = 0 b 1 2 -- - input line shift 1 2 -- - scale increment + yscy[15:0] 64 ------------------------------ - 16 + == c 1 2 -- - scale increment yscy[15:0] 64 ------------------------------ - == handbook, full pagewidth mhb548 ?ld 1 ?ld 2 upper lower ?ld 1 ?ld 2 case up-up case lo-lo ?ld 1 ?ld 2 case up-lo case lo-up a b c d
2000 mar 15 50 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h in tables 12 and 13 pho is a usable common phase offset. please notice that the equations of fig.29 are producing an interpolated output also for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field (see table 12). if there is no need for up-lo and lo-up conversion and the input field id is the reference for the back-end operation, then it is up-lo = up-up and lo-up = lo-lo and the 1 2 line phase shift (pho + 16) can be skipped. this case is listed in table 13. the SAA7114h supports 4 phase offset registers per task and component (luminance and chrominance). the value of 20h represents a phase shift of one line. the registers are assigned to the following events; e.g. subaddresses b8h to bbh: b8h: 00 = input field id 0, task status bit 0 (toggle status, see section 8.3.1.3) b9h: 01 = input field id 0, task status bit 1 bah: 10 = input field id 1, task status bit 0 bbh: 11 = input field id 1, task status bit 1. dependent on the input signal (interlaced or non-interlaced) and the task processing (50 hz or field reduced processing with one or two tasks, see examples in section 8.3.1.3), also other combinations may be possible, but the basic equations are the same. table 12 examples for vertical phase offset usage: global equations input field under processing output field interpreted as used abbreviation equation for phase offset calculation (decimal values) upper input lines upper output lines up-up pho + 16 upper input lines lower output lines up-lo lower input lines upper output lines lo-up pho lower input lines lower output lines lo-lo pho yscy[15:0] 64 ------------------------------ - 16 ++ pho yscy[15:0] 64 ------------------------------ - +
2000 mar 15 51 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 13 vertical phase offset usage; assignment of the phase offsets notes 1. case 1: ofidc[90h[6]] = 0; scaler input field id as output id; back-end interprets output field id at logic 0 as upper output lines. 2. case 2: ofidc[90h[6]] = 1; task status bit as output id; back-end interprets output field id at logic 0 as upper output lines. 3. case 3: ofidc[90h[6]] = 1; task status bit as output id; back-end interprets output field id at logic 1 as upper output lines. detected input field id task status bit vertical phase offset case equation to be used 0 = upper lines 0 ypy(c)0[7:0] case 1 (1) up-up (pho) case 2 (2) up-up case 3 (3) up-lo 0 = upper lines 1 ypy(c)1[7:0] case 1 up-up (pho) case 2 up-lo case 3 up-up 1 = lower lines 0 ypy(c)2[7:0] case 1 lo-lo case 2 lo-up case 3 lo-lo 1 = lower lines 1 ypy(c)3[7:0] case 1 lo-lo case 2 lo-lo case 3 lo-up pho yscy[15:0] 64 ------------------------------ - 16 C + ? ?? pho yscy[15:0] 64 ------------------------------ - 16 C + ? ??
2000 mar 15 52 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.4 vbi-data decoder and capture (subaddresses 40h to 7fh) the SAA7114h contains a versatile vbi-data decoder. the implementation and programming model accords to the vbi-data slicer built in the multimedia video data acquisition circuit saa5284. the circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them to bytes. the result is buffered into a dedicated vbi-data fifo with a capacity of 2 56 bytes (2 14 dwords). the clock frequency, signals source, field frequency, accepted error count must be defined in subaddress 40h. the supported vbi-data standards are shown in table 14. for lines 2 to 24 of a field, per vbi line, 1 of 16 standards can be selected (lcr24_[7:0] to lcr2_[7:0] in 57h[7:0] to 41h[7:0]: 23 2 4 bit programming bits). the definition for line 24 is valid for the rest of the corresponding field, normally no text data (= video data) should be selected there (lcr24_[7:0] = ffh) to stop the activity of the vbi-data slicer during active video. to adjust the slicers processing to the input signal source, there are offsets in horizontal and vertical direction available: parameters hoff[10:0]5bh[2:0]59h[7:0], voff[8:0]5bh[4]5ah[7:0] and foff[5bh[7]]). contrary to the scalers counting, the slicers offsets are defining the position of the h and v trigger events related to the processed video field. the trigger events are the falling edge of href and the falling edge of v123 from the decoder processing part. the relation of these programming values to the input signal and the recommended values can be seen in tables 4 to 7. table 14 data types supported by the data slicer block dt[3:0] 62h[3:0] standard type data rate (mbits/s) framing code fc window ham check 0000 teletext eurowst, ccst 6.9375 27h wst625 always 0001 european closed caption 0.500 001 cc625 0010 vps 5 9951h vps 0011 wide screen signalling bits 5 1e3c1fh wss 0100 us teletext (wst) 5.7272 27h wst525 always 0101 us closed caption (line 21) 0.503 001 cc525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text optional 1001 vitc/ebu time codes (europe) 1.8125 programmable vitc625 1010 vitc/smpte time codes (usa) 1.7898 programmable vitc625 1011 reserved 1100 us nabts 5.7272 programmable nabts optional 1101 moji (japanese) 5.7272 programmable (a7h) japtext 1110 japanese format switch (l20/22) 5 programmable open 1111 no sliced data transmitted (video data selected) 5 none disable
2000 mar 15 53 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.5 image port output formatter (subaddresses 84h to 87h) the output interface consists of a fifo for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the i-port and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream and the accompanied reference and supporting information. the clock for the output interface can be derived from an internal clock, decoder, expansion port, or an externally provided clock which is appropriate for e.g. vga and frame buffer. the clock can be up to 33 mhz. the scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84h and 85h: output field id start and end of vertical active video range, start and end of active video line data qualifier or gated clock actually activated programming page (if conlh is used) threshold controlled fifo filling flags (empty, full, filled) sliced data marker. the disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. clock cycles with invalid data on the i-port data bus (including the hpd pins in 16-bit output mode) are marked with code 00h. the output interface also arbitrates the transfer between scaled video data and sliced text data over the i-port output. the bits vitx1 and vitx0 (subaddress 86h) are used to control the arbitration. as further operation the serialization of the internal 32-bit dwords to 8-bit or optional 16-bit output, as well as the insertion of the extended itu 656 codes (sav/eav for video data, anc or sav/eav codes for sliced text data) are done here. for handshake with the vga controller, or other memory or bus interface circuitry, programmable fifo flags are provided (see section 8.5.2). 8.5.1 s caler output formatter ( subaddresses 93h and c3h) the output formatter organizes the packing into the output fifo. the following formats are available: yuv 4:2:2, yuv4:1:1, yuv4:2:0, yuv4:1:0, y only (e.g. for raw samples). the formatting is controlled by fsi[2:0]93h[2:0], foi[1:0]93h[4:3] and fysk[93h[5]]. the data formats are defined on dwords, or multiples, and are similar to the video formats as recommended for pci multimedia applications (compare saa7146a), but planar formats are not supported. fsi[2:0] defines the horizontal packing of the data, foi[1:0] defines, how many y only lines are expected, before a y/c line will be formatted. if fysk is set to logic 0 preceding y only lines will be skipped, and output will always start with a y/c line. additionally the output formatter limits the amplitude range of the video data (controlled by illv[85h[5]]); see table 17. table 15 byte stream for different output formats table 16 explanation to table 15 output format byte sequence for 8-bit output modes yuv4:2:2 c b 0y0c r 0y1c b 2y2c r 2y3c b 4y4c r 4y5 c b 6y6 yuv4:1:1 c b 0y0c r 0y1c b 4y2c r 4 y3y4 y5y6 y7 c b 8y8 y only y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 name explanation c b n u (b - y) colour difference component, pixel number n = 0, 2, 4 to 718 yn y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 c r n v (r - y) colour difference component, pixel number n = 0, 2, 4 to 718
2000 mar 15 54 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 17 limiting range on i-port limit step illv[85h[5]] valid range suppressed codes (hexadecimal value) decimal value hexadecimal value lower range upper range 0 1 to 254 01 to fe 00 ff 1 8 to 247 08 to f7 00 to 07 f8 to ff 8.5.2 v ideo fifo ( subaddress 86h) the video fifo at the scaler output contains 32 dwords. that corresponds to 64 pixels in 16-bit yuv 4:2:2 format. but as the entire scaler can act as pipeline buffer, the actually available buffer capacity for the image port is much higher, and can exceed beyond a video line. the image port, and the video fifo, can operate with the video source clock (synchronous mode) or with externally provided clock (asynchronous, and burst mode), as appropriate for the vga controller or attached frame buffer. the video fifo provides 4 internal flags, reporting to which extent the fifo is actually filled. these are: the fifo almost empty (fae) flag the fifo combined flag (fcf) or fifo filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark the fifo almost full (faf) flag the fifo overflow (fovl) flag. the trigger levels for fae and faf are programmable by ffl[1:0]86h[3:2] (16, 24, 28, full) and fel[1:0]86h[1:0] (16, 8, 4, empty). the state of this flag can be seen on the pins igp0 or igp1. the pin mapping is defined by subaddresses 84h and 85h (see section 9.5). 8.5.3 t ext fifo in the text fifo the data of the terminal vbi-data slicer are collected before the transmission over the i-port is requested (normally before the video window starts). it is partitioned into two fifo sections. a complete line is filled into the fifo, before a data transfer is requested. so normally, one line text data is ready for transfer, while the next text line is collected. so sliced text data are delivered as a block of qualified data, without any qualification gaps in the byte stream of the i-port. the decoded vbi-data is collected in the dedicated vbi-data fifo. after capture of a line is completed, the fifo can be streamed through the image port, preceded by a header, telling line number and standard. the vbi-data period can be signalled via the sliced data flag on pin igp0 or igp1. the decoded vbi-data is lead by the itu ancillary data header (did[5:0]5dh[5:0] at value <3eh) or by sav/eav codes selectable by did[5:0] at value 3eh or 3fh. igp0 or igp1 is set, if the first byte of the anc header is valid on the i-port bus. it is reset, if an sav occurs. so it may frame multiple lines of text data output, in case video processing starts with a distance of several video lines to the region of text data. valid sliced data from the text fifo are available on the i-port as long as the igp0 or igp1 flag is set and the data qualifier is active on pin idq. the decoded vbi-data are presented in two different data formats, controlled by bit recode. recode = 1: values 00h and ffh will be recoded to even parity values 03h and fch recode = 0: values 00h and ffh may occur in the data stream as detected. 8.5.4 v ideo and text arbitration ( subaddress 86h) sliced text data and scaled video data are transferred over the same bus, the i-port. the mixed transfer is controlled by an arbitration circuitry. if the video data are transferred without any interrupt and the video fifo does not need to buffer any output pixel, the text data are inserted after an end of a scaled video line, normally during the blanking interval of the video.
2000 mar 15 55 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.5.5 d ata stream coding and reference signal generation ( subaddresses 84h, 85h and 93h) as h and v reference signals are logic 1, active gate signals are generated, which are framing the transfer of the valid output data. alternative to the gates, h and v trigger pulses are generated on the rising edges of the gates. due to the dynamic fifo behaviour of the complete scaler path, the output signal timing has no fixed timing relation to the real-time input video stream. so fixed propagation delays, in therms of clock cycles, related to the analog input can not be defined. the data stream is accompanied by a data qualifier. additionally invalid data cycles are marked with code 00h. if itu 656 like codes are not wanted, these codes can be suppressed in the output stream. as further option, it is possible to provide the scaler with a gating external signal on pin itrdy. so it is possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. the sketched reference signals and events can be mapped to the i-port output pins idq, igph, igpv, igp0 and igp1. for flexible use the polarities of all the outputs can be modified. the default polarity for the qualifier and reference signals is logic 1 (= active). table 18 shows the relevant and supported sav and eav coding. table 18 sav/eav codes on i-port notes 1. the leading byte sequence is: ffh-00h-00h. 2. the msb of the sav/eav code byte is controlled by: a) scaler output data: task a t msb = conlh (90h[7]); task b t msb = conlh (c0h[7]). b) vbi-data slicer output data: did[5:0]5dh[5:0] = 3eh t msb = 1; did[5:0]5dh[5:0] = 3fh t msb = 0. event description sav/eav codes on i-port (1) (hex) comment msb (2) of sav/eav byte = 0 msb (2) of sav/eav byte = 1 field id = 0 field id = 1 field id = 0 field id = 1 next pixel is first pixel of any active line 0e 49 80 c7 href = active; vref = active previous pixel was last pixel of any active line, but not the last 13 54 9d da href = inactive; vref = active next pixel is first pixel of any v-blanking line 25 62 ab ec href = active; vref = inactive previous pixel was last pixel of the last active line or of any v-blanking line 38 7f b6 f1 href = inactive; vref = inactive no valid data, dont capture and dont increment pointer 00 idq pin inactive
2000 mar 15 56 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 19 explanation to fig.30 notes 1. inverted ep (bit 7); for ep see note 2. 2. even parity (bit 6) of bits 5 to 0. 3. odd parity (bit 7) of bits 6 to 0. name explanation sav start of active data; see table 20 sdid sliced data identi?cation: nep (1) , ep (2) , sdid5 to sdid0, freely programmable via i 2 c-bus subaddress 5eh, d5 to d0, e. g. to be used as source identi?er dc dword count: nep (1) , ep (2) , dc5 to dc0. dc describes the number of succeeding 32-bit words: for sav/eav mode dc is fixed to 11 dwords (byte value 4bh) for anc mode it is: dc = 1 4 (c + n), where c = 2 (the two data identification bytes idi1 and idi2) and n = number of decoded bytes according to the chosen text standard. note that the number of valid bytes inside the stream can be seen in the bc byte. idi1 internal data identi?cation 1: op (3) , fid (?eld 1 = 0, ?eld 2 = 1), linenumber8 to linenumber3 = dword 1 byte 1; see table 20 idi2 internal data identi?cation 2: op (3) , linenumber2 to linenumber0, datatype3 to datatype0 = dword 1 byte 2; see table 20 d n_m dword number n , byte number m d dc_4 last dword byte 4, note: for sav/eav framing dc is ?xed to 0bh, missing data bytes are ?lled up; the ?ll value is a0h cs the check sum byte, the checksum is accumulated from the sav (respectively did) byte to the d dc_4 byte bc number of valid sliced bytes counted from the idi1 byte eav end of active data; see table 20 mhb549 00 00 ff 00 00 sav sdid dc idi1 idi2 d 1_3 d 1_4 d 2_1 d dc_3 d dc_4 cs bc ff 00 00 eav 00 00 ... ... ... ... d 1_2 d 1_1 ... ff 00 00 eav 00 ff ff did sdid dc idi1 idi2 d 1_3 d 1_4 d dc_3 d dc_4 cs bc 00 00 ... anc header internal header sliced data anc data output is only filled up to the dword boundary timing reference code invalid data or end of raw vbi line timing reference code internal header sliced data invalid data and filling data fig.30 sliced data formats on the i-port in 8-bit mode. anc header active for did (subaddress 5dh) <3eh
2000 mar 15 57 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 20 bytes stream of the data slicer notes 1. nep = inverted ep (see note 2). 2. ep = even parity of bits 5 to 0. 3. fid = 0: field 1; fid = 1: field 2. 4. i1 = 0 and i0 = 0: before line 1; i1 = 0 and i0 = 1: lines 1 to 23; i1 = 1 and i0 = 0: after line 23; i1 = 1 and i0 = 1: line 24 to end of field. 5. subaddress 5dh at 3eh and 3fh are used for itu 656 like sav/eav header generation; recommended value. 6. v = 0: active video; v = 1: blanking. 7. h = 0: start of line; h = 1: end of line. 8. dc = data count in dwords according to the data type. 9. op = odd parity of bits 6 to 0. 10. ln = line number. 11. dt = data type according to table. nick name comment d7 d6 d5 d4 d3 d2 d1 d0 did, sav, eav subaddress 5dh = 00h nep (1) ep (2) 0 1 0 fid (3) i1 (4) i0 (4) subaddress 5dh; d5=1 nep ep 0 d4[5dh] d3[5dh] d2[5dh] d1[5dh] d0[5dh] subaddress 5dh d5 = 3eh; note 5 1 fid (3) v (6) h (7) p3 p2 p1 p0 subaddress 5dh d5 = 3fh; note 5 0 fid (3) v (6) h (7) p3 p2 p1 p0 sdid programmable via subaddress 5eh nep ep d5[5eh] d4[5eh] d3[5eh] d2[5eh] d1[5eh] d0[5eh] dc (8) nep ep (2) dc5 dc4 dc3 dc2 dc1 dc0 idi1 op (9) fid (3) ln8 (10) ln7 (10) ln6 (10) ln5 (10) ln4 (10) ln3 (10) idi2 op ln2 (10) ln1 (10) ln0 (10) dt3 (11) dt2 (11) dt1 (11) dt0 (11) cs check sum byte cs6 cs6 cs5 cs4 cs3 cs2 cs1 cs0 bc valid byte count op 0 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0
2000 mar 15 58 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.6 audio clock generation (subaddresses 30h to 3fh) SAA7114h incorporates generation of a field locked audio clock, as an auxiliary function for video capture. an audio sample clock, that is locked to the field frequency, makes sure that there is always the same predefined number of audio samples associated with a field, or a set of fields. that ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), mpeg or other compression, or non-linear editing. 8.6.1 m aster audio clock the audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. the master audio clock is defined by the parameters: audio master clocks per field, acpf[17:0]32h[1:0]31h[7:0]30h[7:0] according to the equation: audio master clocks nominal increment, acni[21:0]36h[5:0]35h[7:0]34h[7:0] according to the equation: see table 21 for examples. remark : for standard applications the synthesized audio clock amclk can be used directly as master clock and as input clock for port amxclk (short cut) to generate asclk and alrclk. for high-end applications it is recommended to use an external analog pll circuit to enhance the performance of the generated audio clock. acpf[17:0] round audio frequency field frequency ------------------------------------------ ? ?? = acni21:0] round audio frequency crystal frequency -------------------------------------------- - 2 23 ? ?? = table 21 programming examples for audio master clock generation xtalo (mhz) field (hz) acpf acni decimal hex decimal hex amclk = 256 48 khz (12.288 mhz) 32.11 50 245760 3c000 3210190 30fbce 59.94 205005 320cd 3210190 30fbce 24.576 50 ---- 59.94 ---- amclk = 256 44.1 khz (11.2896 mhz) 32.11 50 225792 37200 2949362 2d00f2 59.94 188348 2dfbc 2949362 2d00f2 24.576 50 225792 37200 3853517 3acccd 59.94 188348 2dfbc 3853 517 3acccd amclk = 256 32 khz (8.192 mhz) 32.11 50 163840 28000 2140127 20a7df 59.94 136670 215de 2140127 20a7df 24.576 50 163840 28000 2796203 2aaaab 59.94 136670 215de 2796203 2aaaab
2000 mar 15 59 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 8.6.2 s ignals asclk and alrclk two binary divided signals asclk and alrclk are provided for slower serial digital audio signal transmission and for channel-select. the frequencies of these signals are defined by the parameters: sdiv[5:0]38h[5:0] according to the equation: t lrdiv[5:0]39h[5:0] according to the equation: t see table 22 for examples. f asclk f amxclk sdiv 1 + () 2 ------------------------------------- - = sdiv[5:0] f amxclk 2f asclk ------------------- - 1 C = f alrclk f asclk lrdiv 2 -------------------------- - = lrdiv[5:0] f asclk 2f alrclk ---------------------- - = table 22 programming examples for asclk/alrclk clock generation amxclk (mhz) asclk (khz) sdiv alrclk (khz) lrdiv decimal hex decimal hex 12.288 1536 3 03 48 16 10 768 7 07 8 08 11.2896 1411.2 3 03 44.1 16 10 2822.4 1 01 32 10 8.192 1024 3 03 32 16 10 2048 1 01 32 10 8.6.3 o ther control signals further control signals are available to define reference clock edges and vertical references: apll[3ah[3]]; audio pll mode: 0: pll closed 1: pll open amvr[3ah[2]]; audio master clock vertical reference: 0: internal v 1: external v lrph[3ah[1]]; alrclk phase 0: invert asclk, alrclk edges triggered by falling edge of asclk 1: dont invert asclk, alrclk edges triggered by rising edge of asclk scph[3ah[0]]; asclk phase: 0: invert amxclk, asclk edges triggered by falling edge of amxclk 1: dont invert amxclk, asclk edges triggered by rising edge of amxclk
2000 mar 15 60 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 9 input/output interfaces and ports the SAA7114h has 5 different i/o interfaces: analog video input interface, for analog cvbs and/or y and c input signals audio clock port digital real-time signal port (rt port) digital video expansion port (x-port), for unscaled digital video input and output digital image port (i-port) for scaled video data output and programming digital host port (h-port) for extension of the image port or expansion port from 8 to 16-bit. 9.1 analog terminals the SAA7114h has 6 analog inputs ai21 to ai24, ai11 and ai12 for composite video cvbs or s-video y/c signal pairs. additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. there are no peripheral components required other than these decoupling capacitors and 18 w /56 w termination resistors, one set per connected input signal (see also application example in fig.40). two anti-alias filters are integrated, and self adjusting via the clock frequency. clamp and gain control for the two adcs are also integrated. an analog video output pin aout is provided for testing purposes. table 23 analog pin description symbol pin i/o description bit ai24 to ai21 10, 12, 14 and 16 i analog video signal inputs, e.g. 2 cvbs signals and two y/c pairs can be connected simultaneously mode3 to mode0 ai12 and ai11 18 and 20 aout 22 o analog video output, for test purposes aosl1 and aosl0 ai1d and ai2d 19 and 13 i analog reference pins for differential adc operation - 9.2 audio clock signals the SAA7114h also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow pll. this ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. an audio master clock amclk and two divided clocks asclk and alrclk are generated; asclk: can be used as audio serial clock alrclk: audio left/right channel clock. the ratios are programmable, see also section 8.6. table 24 audio clock pin description symbol pin i/o description bit amclk 37 o audio master clock output acpf[17:0]32h[1:0]31h[7:0]30h[7:0] and acni[21:0]36h[5:0]35h[7:0]34h[7:0] amxclk 41 i external audio master clock input for the clock division circuit, can be directly connected to output amclk for standard applications - asclk 39 o serial audio clock output, can be synchronized to rising or falling edge of amxclk sdiv[5:0]38h[5:0] and scph[3ah[0]] alrclk 40 o audio channel (left/right) clock output, can be synchronized to rising or falling edge of asclk lrdiv[5:0]39h[5:0] and lrph[3ah[1]]
2000 mar 15 61 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 9.3 clock and real-time synchronization signals for the generation of the line-locked video (pixel) clock llc, and of the frame locked audio serial bit clock, a crystal accurate frequency reference is required. an oscillator is built in, for fundamental or third harmonic crystals. the supported crystal frequencies are 32.11 or 24.576 mhz (defined during reset by strapping pin alrclk). alternatively pin xtali can be driven from an external single ended oscillator. the crystal oscillation can be propagated as clock to other ics in the system via pin xout. the line-locked clock (llc) is the double pixel clock of nominal 27 mhz. it is locked to the selected video input, generating baseband video pixels according to itu recommendation 601 . in order to support interfacing circuitries, a direct pixel clock llc2 is also provided. the pins for line and field timing reference signals are rtco, rts1 and rts0. various real-time status information can be selected for the rts pins. the signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7114h. the function of the rts1 and rts0 pins can be defined by bits rtse1[3:0]12h[7:4] and rtse0[3:0]12h[3:0]. table 25 clock and real-time synchronization signals symbol pin i/o description bit crystal oscillator xtali 7 i input for crystal oscillator, or reference clock - xtalo 6 o output of crystal oscillator - xout 4 o reference (crystal) clock output drive (optional) xtoute[14h[3]] real-time signals (rt port) llc 28 o line-locked clock, nominal 27 mhz, double pixel clock locked to the selected video input signal - llc2 29 o line-locked pixel clock, nominal 13.5 mhz - rtco 36 o real-time control output, transfers real-time status information supporting rtc level 3.1 (see external document rtc functional description , available on request) - rts0 34 o real-time status information line 0, can be programmed to carry various real-time informations (see table 55) rtse0[3:0]12h[3:0] rts1 35 o real-time status information line 1, can be programmed to carry various real-time informations (see table 56) rtse1[3:0]12h[7:4]
2000 mar 15 62 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 9.4 video expansion port (x-port) the expansion port is intended for transporting video streams image data from other digital video circuits like mpeg encoder/decoder and video phone codec, to the image port (i-port). the expansion port consists of two groups of signals/pins: 8-bit data, i/o, regularly components video yuv4:2:2, i.e. c b -y-c r -y, byte serial, exceptionally raw video samples (e.g. adc test). in input mode the data bus can be extended to 16-bit by the pins hpd7 to hpd0. clock, synchronization and auxiliary signals, accompanying the data stream, i/o. as output, these are direct copies of the decoder signals. the data transfers through the expansion port represent a single d1 port, with half duplex mode. the sav and eav codes may be inserted optionally for data input (controlled by bit xcode[92h[3]]). the input/output direction is switched for complete fields, only. table 26 signals dedicated to the expansion port symbol pin i/o description bit xpd7 to xpd0 81, 82, 84 to 87, 89 and 90 i/o x-port data: in output mode controlled by decoder section, data format see table 27; in input mode yuv4:2:2 ser ial input data or luminance part of a 16-bit yuv 4 : 2 : 2 input ofts[2:0]13h[2:0]; 91h[7:0] and c1h[7:0] xclk 94 i/o clock at expansion port: if output, then copy of llc; as input normally a double pixel clock of up to 32 mhz or a gated clock (clock gated with a quali?er) xcks[92h[0]] xdq 95 i/o data valid ?ag of the expansion port input (quali?er): if output, then decoder (href and vgate) gate (see fig.23) - xrdy 96 o data request ?ag = ready to receive, to work with optional buffer in external device, to prevent internal buffer over?ow; second function: input related task ?ag a/b xrqt[83h[2]] xrh 92 i/o horizontal reference signal for the x-port: as output: href or hs from the decoder (see fig.23); as input: a reference edge for horizontal input timing and a polarity for input ?eld id detection can be de?ned xrhs[13h[6]], xfdh[92h[6]] and xdh[92h[2]] xrv 91 i/o vertical reference signal for the x-port: as output: v123 or ?eld id from the decoder, see figs 21 and 22; as input: a reference edge for vertical input timing and for input ?eld id detection can be de?ned xrvs[1:0]13h[5:4], xfdv[92h[7]] and xdv[1:0]92h[5:4] xtri 80 i port control: switches x-port input 3-state xpe[1:0]83h[1:0]
2000 mar 15 63 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 9.4.1 x- port configured as output if data output is enabled at the expansion port, then the data stream from the decoder is presented. the data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers lcr2 to lcr24; see table 3. in contrast to the image port, the sliced data format is not available on the expansion port. instead, raw cvbs samples are always transferred if any sliced data type is selected. following are some details of data types on the expansion port: active video (data type 15) contains component yuv4:2:2 signal, 720 active pixels per line. the amplitude and offsets are programmable via dbri7 to dbri0, dcon7 to dcon0, dsat7 to dsat0, offu1, offu0, offv1 and offv0. for nominal levels see fig.17. test line (data type 6) is similar to active video format, with some constraints within the data processing: C adaptive chrominance comb filter, vertical filter (chrominance comb filter for ntsc standards, pal phase error correction) within the chrominance processing are disabled C adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing. this data type is defined for future enhancements. it could be activated for lines containing standard test signals within the vertical blanking period. currently the most sources do not contain test lines. for nominal levels see fig.17. raw samples (data types 0 to 5 and 7 to 14): uv-samples are similar to data type 6, but cvbs samples are transferred instead of processed luminance samples within the y time slots. the amplitude and offset of the cvbs signal is programmable via rawg7 to rawg0 and rawo7 to rawo0; see chapter 15 i 2 c-bus description, tables 62 and 63. for nominal levels see fig.18. the relation of lcr programming to line numbers is described in section 8.2, see tables 4 to 7. the data type selections by lcr are overruled by setting ofts2 (subaddress 13h bit 2) = 1. this setting is mainly intended for device production test. the vpo-bus carries the upper or lower 8 bits of the two adcs dependent on ofts[1:0]13h[1:0] settings; see table 57. the output configuration is done via mode[3:0]02h[3:0] settings; see table 39. if a yc mode is selected, the expansion port carries the multiplexed output signals of both adcs, in cvbs mode the output of only one adc. no timing reference codes are generated in this mode. remark : the lsbs (bit 0) of the adcs are also available on pin rts0. for details see table 55. the sav/eav timing reference codes define start and end of valid data regions. during horizontal blanking period between eav and sav the itu-blanking code sequence - 80 - 10 - 80 - 10 -... is transmitted. the position of the f-bit is constant according to itu 656 (see tables 29 and 30). the v-bit can be generated in two different ways (see tables 29 and 30) controlled via ofts1 and ofts0, see table 57. f and v bits change synchronously with the eav code. table 27 data format on the expansion port notes 1. the generation of the timing reference codes can be suppressed by setting ofts[2:0] to 010, see table 57. in this event the code sequence is replaced by the standard - 80 - 10 - blanking values. 2. if raw samples or sliced data are selected by the line control registers (lcr2 to lcr24), the y-samples are replaced by cvbs samples. blanking period timing reference code (hex) (1) 720 pixels yuv 4:2:2 data (2) timing reference code (hex) (1) blanking period ... 80 10 ff 00 00 sav c b 0y0c r 0y1c b 2 y2 ... c r 718 y719 ff 00 00 eav 80 10 ...
2000 mar 15 64 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 28 sav/eav format on expansion port xpd7 to xpd0 table 29 525 lines/60 hz vertical timing table 30 625 lines/50 hz vertical timing bit 7 bit 6 (f) bit 5 (v) bit 4 (h) bit 3 (p3) bit 2 (p2) bit 1 (p1) bit 0 (p0) 1 ?eld bit vertical blanking bit format reserved; evaluation not recommended (protection bits according to itu 656) 1st field: f = 0 2nd field: f = 1 vbi: v = 1 active video: v = 0 h = 0 in sav format h = 1 in eav format for vertical timing see tables 29 and 30 line number f (itu 656) v ofts[2:0] = 000 (itu 656) ofts[2:0] = 001 1 to 3 1 1 according to selected vgate position type via vsta and vsto (subaddresses 15h to 17h); see tables 59 to 61 4to19 0 1 20 0 0 21 0 0 22 to 261 0 0 262 0 0 263 0 0 264 and 265 0 1 266 to 282 1 1 283 1 0 284 1 0 285 to 524 1 0 525 1 0 line number f (itu 656) v ofts[2:0] = 000 (itu 656) ofts[1:0] = 10 1 to 22 0 1 according to selected vgate position type via vsta and vsto (subaddresses 15h to 17h); see tables 59 to 61 23 0 0 24 to 309 0 0 310 0 0 311 and 312 0 1 313 to 335 1 1 336 1 0 337 to 622 1 0 623 1 0 624 and 625 1 1
2000 mar 15 65 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 9.4.2 x- port configured as input if data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from expansion port (controlled by bit scsrc[1:0]91h[5:4]). byte serial yuv 4:2:2, or subsets for other sampling schemes, or raw samples from an external adc may be input (see also bits fsc[2:0]91h[2:0]). the input stream must be accompanied by an external clock xclk, qualifier xdq and reference signals xrh and xrv. instead of the reference signal, embedded sav and eav codes according to itu 656 are also accepted. the protection bits are not evaluated. xrh and xrv carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. the field id of the input video stream is carried in the phase (edge) of xrv and state of xrh, or directly as fs (frame sync, odd/even signal) on the xrv pin (controlled by xfdv[92h[7]], xfdh[92h[6]] and xdv1[92h[5]]). the trigger events on xrh (rising/falling edge) and xrv (rising/falling/both edges) for the scalers acquisition window are defined by xdv[1:0]92h[5:4] and xdh[92h[2]]. also the signal polarity of the qualifier can be defined (bit xdq[92h[1]]). alternatively to a qualifier, the input clock can be applied to a gated clock (means clock gated with a data qualifier, controlled by bit xcks[92h[0]]). in this event, all input data will be qualified. 9.5 image port (i-port) the image port transfers data from the scaler as well as from the vbi-data slicer, if so selected (maximum 33 mhz). the reference clock is available at the iclk pin, as output, or as input (maximum 33 mhz). as output, iclk is derived from the locked decoder or expansion port input clock. the data stream from the scaler output is normally discontinuous. therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin idq. for pin constrained applications the idq pin can be programmed to function as gated clock output (bit icks2[80h[2]]). the data formats at the image port are defined in dwords of 32 bits (4 bytes), like the related fifo structures. but the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins hpd7 to hpd0 are used for chrominance data. the four bytes of the dwords are serialized in words or bytes. available formats are: yuv4:2:2, yuv4:1:1, raw samples decoded vbi-data. for handshake with the receiving vga controller, or other memory or bus interface circuitry, f, h and v reference signals and programmable fifo flags are provided. the information will be provided on pins igp0, igp1, igph and igpv. the functionality on this pins is controlled via subaddresses 84h and 85h. vbi-data is collected over an entire line in its own fifo, and transferred as an uninterrupted block of bytes. decoded vbi-data can be signed by the vbi flag on pin igp0/1. as scaled video data and decoded vbi-data may come from different and asynchronous sources, an arbitration scheme is needed. normally vbi-data slicer has priority. the image port consists of the pins and/or signals, as listed in table 31. for pin constrained applications, or interfaces, the relevant timing and data reference signals can also get encoded into the data stream. therefore the corresponding pins do not need to get connected. the minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. the inserted codes are defined in close relation to the itu/ccir-656 (d1) recommendation, where possible. the following deviations from itu 656 recommendation are implemented at SAA7114hs image port interface: sav and eav codes are only present in those lines, where data is to be transferred, i.e. active video lines, or vbi-raw samples, no codes for empty lines there may be more or less than 720 pixels between sav and eav data content and number of clock cycles during horizontal and vertical blanking is undefined, and may be not constant data stream may be interleaved with not-valid data codes, 00h, but sav and eav 4-byte codes are not interleaved with not-valid data codes there may be an irregular pattern of not-valid data, or idq, and as a result, c b -y-c r - y - is not in a fixed phase to a regular clock divider
2000 mar 15 66 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h vbi-raw sample streams are enveloped with sav and eav, like normal video decoded vbi-data is transported as ancillary (anc) data, two modes: C direct decoded vbi-data bytes (8-bit) are directly placed in the anc data field, 00h and ffh codes may appear in data block (violation to ccir-656) C recoded vbi-data bytes (8-bit) directly placed in anc data field, 00h and ffh codes will be recoded to even parity codes 03h and fch to suppress invalid ccir-656 codes. there are no empty cycles in the ancillary code and its data field. the data codes 00h and ffh are suppressed (changed to 01h or feh respectively) in active video stream, as well as in vbi-raw sample stream (vbi pass-through). optionally the number range can be limited further. table 31 signals dedicated to the image port symbol pin i/o description bit ipd7 to ipd0 54 to 57 and 59 to 62 i/o i-port data icode[93h[7]], iswp[1:0]85h[7:6] and ipe[1:0]87[1:0] iclk 45 i/o continuous reference clock at image port, can be input or output, as output decoder llc or xclk from x-port icks[1:0]80h[1:0] and ipe[1:0]87h[1:0] idq 46 o data valid ?ag at image port, quali?er, with programmable polarity; secondary function: gated clock icks2[80h[2]], idqp[85h[0]] and ipe[1:0]87h[1:0] igph 53 o horizontal reference output signal, copy of the h-gate signal of the scaler, with programmable polarity; alternative functions: hreset pulse idh[1:0]84h[1:0], irhp[85h[1]] and ipe[1:0]87h[1:0] igpv 52 o vertical reference output signal, copy of the v-gate signal of the scaler, with programmable polarity; alternative functions: vreset pulse idv[1:0]84h[3:2], irvp[85h[2]] and ipe[1:0]87h[1:0] igp1 49 o general purpose output signal for i-port idg12[86h[4]], idg1[1:0]84h[5:4], ig1p[85h[3]] and ipe[1:0]87h[1:0] igp0 48 o general purpose output signal for i-port idg02[86h[5]], idg0[1:0]84h[7:6], ig0p[85h[4]] and ipe[1:0]87h[1:0] itrdy 42 i target ready input signals - itri 47 i port control, switches i-port into 3-state ipe[1:0]87h[1:0]
2000 mar 15 67 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 9.6 host port for 16-bit extension of video data i/o (h-port) the h-port pins hpd can be used for extension of the data i/o paths to 16-bit. functional priority has the i-port. if i8_16[93h[6]] is set to logic 1 the output drivers of the h-port are enabled dependent on the i-port enable control. for i8_16 = 0, the hpd output is disabled. table 32 signals dedicated to the host port 9.7 basic input and output timing diagrams i-port and x-port 9.7.1 i- port output timing the following diagrams are sketching the output timing via the i-port. igph and igpv are sketched as logic 1 active gate signals. if reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. valid data is accompanied by the output data qualifier on pin idq. in addition invalid cycles are marked with output code 00h. the idq output pin may be defined to be a gated clock output signal (iclk and internal idq). 9.7.2 x- port input timing at the x-port the input timing requirements are the same as sketched for the i-port output. but different to this: it is not necessary to mark invalid cycles with a 00h code no constraints on the input qualifier (can be a random pattern) xclk may be a gated clock (xclk and external xdq). remark : all timings illustrated in figs 31 to 37 are given for an uninterrupted output stream (no handshake with the external hardware). symbol pin i/o description bit hpd7 to hpd0 64 to 67 and 69 to 72 i/o 16-bit extension for digital i/o (chrominance component) ipe[1:0]87h[1:0], itri[8fh[6]] and i8_16[93h[6]] fig.31 output timing i-port for serial 8-bit data at start of a line (icode = 1). handbook, full pagewidth ipd [ 7:0 ] igph idq iclk 00 ff 00 00 sav 00 c b y c r y00 c b y c r y00 mhb550
2000 mar 15 68 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.32 output timing i-port for serial 8-bit data at start of a line (icode = 0). handbook, full pagewidth ipd [ 7:0 ] igph idq iclk 00 c b y c r y00 c b y c r y00 mhb551 fig.33 output timing i-port for serial 8-bit data at end of a line (icode = 1). handbook, full pagewidth ipd [ 7:0 ] igph idq iclk 00 c b y c r y00 c b y c r y00ff0000eav00 mhb552
2000 mar 15 69 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.34 output timing i-port for serial 8-bit data at end of a line (icode = 0). handbook, full pagewidth ipd [ 7:0 ] igph idq iclk 00 c b y c r y00 c b y c r y00 mhb553 fig.35 output timing for 16-bit data output via i-port and h-port with codes (icode = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle. handbook, full pagewidth ipd [ 7:0 ] hpd [ 7:0 ] igph idq iclk 00 ff 00 00 y0 y1 00 y2 y3 y n - 1 y n 00 ff 00 00 mhb554 00 00 sav 00 00 c b c b c r c r c r c b 00 00 eav 00
2000 mar 15 70 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.36 h-gate and v-gate output timing. handbook, full pagewidth igpv igph idq mhb555 fig.37 output timing for sliced vbi-data in 8-bit serial output mode (dotted graphs for sav/eav mode). handbook, full pagewidth ipd [ 7:0 ] hpd [ 7:0 ] isld idq iclk 00 00 ff ff did sdid xx yy zz cs bc 00 00 00 mhb556 00 ff 00 sav 00 00 00 bc ff eav
2000 mar 15 71 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 10 boundary scan test the SAA7114h has built in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the SAA7114h follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, intest, sample, clamp and idcode are all supported (see table 33). details about the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) description of the SAA7114h is available on request. table 33 bst instructions supported by the SAA7114h instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. intest this optional instruction allows testing of the internal logic (no customer support available). user1 this private instruction allows testing by the manufacturer (no customer support available). 10.1 initialization of boundary scan circuit the tap (test access port) controller of an ic should be in the reset state (test_logic_reset) when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trst pin low. 10.2 device identi?cation codes a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.38.
2000 mar 15 72 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.38 32 bits of identification code. handbook, full pagewidth mhb557 00000010101 0111000100010100 nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo 31 msb lsb 28 27 12 11 1 0 1 11 limiting values in accordance with the absolute maximum rating system (iec 134); all ground pins connected together and all supply pins connected together. notes 1. maximum: 4.6 v. 2. except pin xtali. 3. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor. 12 thermal characteristics symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.5 +4.6 v v dda analog supply voltage - 0.5 +4.6 v v ia input voltage at analog inputs - 0.5 v dda + 0.5 (1) v v oa output voltage at analog output - 0.5 v dda + 0.5 v v id input voltage at digital inputs and outputs outputs in 3-state; note 2 - 0.5 +5.5 v v od output voltage at digital outputs outputs active - 0.5 v ddd + 0.5 v d v ss voltage difference between v ssan and v ssdn - 100 mv t stg storage temperature - 65 +150 c t amb operating ambient temperature 0 70 c t amb(bias) operating ambient temperature under bias - 10 +80 c v esd electrostatic discharge all pins note 3 - 2000 +2000 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 54 k/w
2000 mar 15 73 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 13 characteristics v ddd = 3.0 to 3.6 v; v dda = 3.1 to 3.5 v; t amb =25 c; timings and levels refer to drawings and conditions illustrated in fig.39; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current x-port 3-state; 8-bit i-port - 90 - ma p d power dissipation digital part - 300 - mw v dda analog supply voltage 3.1 3.3 3.5 v i dda analog supply current aosl1 to aosl0 = 0 cvbs mode - 47 - ma y/c mode - 72 - ma p a power dissipation analog part cvbs mode - 150 - mw y/c mode - 240 - mw p tot(a+d) total power dissipation analog and digital part cvbs mode - 450 - mw y/c mode - 540 - mw p tot(a+d)(pd) total power dissipation analog and digital part in power-down mode ce pulled down to ground - 5 - mw p tot(a+d)(ps) total power dissipation analog and digital part in power-save mode i 2 c-bus controlled via subaddress 88h = 0fh - 75 - mw analog part i clamp clamping current v i = 0.9 v dc - 8 -m a v i(p-p) input voltage (peak-to-peak value) for normal video levels 1 v (p-p), - 3db termination 27/47 w and ac coupling required; coupling capacitor = 22 nf - 0.7 - v ? z i ? input impedance clamping current off 200 -- k w c i input capacitance -- 10 pf a cs channel crosstalk f i < 5 mhz --- 50 db 9-bit analog-to-digital converters b analog bandwidth at - 3db - 7 - mhz f diff differential phase (ampli?er plus anti-alias ?lter bypassed) - 2 - deg g diff differential gain (ampli?er plus anti-alias ?lter bypassed) - 2 - % f clk(adc) adc clock frequency 12.8 - 14.3 mhz
2000 mar 15 74 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h le dc(d) dc differential linearity error - 0.7 - lsb le dc(i) dc integral linearity error - 1 - lsb digital inputs v il(scl,sda) low-level input voltage pins sda and scl - 0.5 - +0.3v ddd v v ih(scl,sda) high-level input voltage pins sda and scl 0.7v ddd - v ddd + 0.5 v v il(xtali) low-level cmos input voltage pin xtali - 0.3 - +0.8 v v ih(xtali) high-level cmos input voltage pin xtali 2.0 - v ddd + 0.3 v v il(n) low-level input voltage all other inputs - 0.3 - +0.8 v v ih(n) high-level input voltage all other inputs 2.0 - 5.5 v i li input leakage current -- 1 m a i li/o i/o leakage current -- 10 m a c i input capacitance i/o at high impedance -- 8pf digital outputs; note 1 v ol(sda) low-level output voltage pin sda sda at 3 ma sink current -- 0.4 v v ol(clk) low-level output voltage for clocks - 0.5 - +0.6 v v oh(clk) high-level output voltage for clocks 2.4 - v ddd + 0.5 v v ol low-level output voltage all other digital outputs 0 - 0.4 v v oh high-level output voltage all other digital outputs 2.4 - v ddd + 0.5 v clock output timing (llc and llc2); note 2 c l output load capacitance 15 - 50 pf t cy cycle time pin llc 35 - 39 ns pin llc2 70 - 78 ns d duty factors for t llch /t llc and t llc2h /t llc2 c l =40pf 40 - 60 % t r rise time llc and llc2 0.2 v to v ddd - 0.2 v -- 5ns t f fall time llc and llc2 v ddd - 0.2 v to 0.2 v -- 5ns t d(llc-llc2) delay time between llc and llc2 output measured at 1.5 v; c l =25pf - 4 - +8 ns symbol parameter conditions min. typ. max. unit
2000 mar 15 75 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h horizontal pll f hor(n) nominal line frequency 50 hz ?eld - 15625 - hz 60 hz ?eld - 15734 - hz d f hor /f hor(n) permissible static deviation -- 5.7 % subcarrier pll f sc(n) nominal subcarrier frequency pal bghi - 4433619 - hz ntsc m - 3579545 - hz pa l m - 3575612 - hz pa l n - 3582056 - hz d f sc lock-in range 400 -- hz crystal oscillator for 32.11 mhz; note 3 f xtal(n) nominal frequency 3rd harmonic - 32.11 - mhz d f xtal(n) permissible nominal frequency deviation -- 70 10 - 6 d f xtal(n)(t) permissible nominal frequency deviation with temperature -- 30 10 - 6 c rystal specification (y1) t amb(x1) operating ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20% - ff c 0 parallel capacitance - 4.3 20% - pf crystal oscillator for 24.576 mhz; note 3 f xtal(n) nominal frequency 3rd harmonic - 24.576 - mhz d f xtal(n) permissible nominal frequency deviation -- 50 10 - 6 d f xtal(n)(t) permissible nominal frequency deviation with temperature -- 20 10 - 6 c rystal specification (y1) t amb(x1) operating ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20% - ff symbol parameter conditions min. typ. max. unit
2000 mar 15 76 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h c 0 parallel capacitance - 3.5 20% - pf clock input timing (xclk) t cy cycle time 31 - 45 ns d duty factors for t llch /t llc 40 50 60 % t r rise time -- 5ns t f fall time -- 5ns data and control signal input timing x-port, related to xclk input t su;dat input data set-up time - 10 - ns t hd;dat input data hold time - 3 - ns clock output timing c l output load capacitance 15 - 50 pf t cy cycle time 35 - 39 ns d duty factors for t xclkh /t xclkl 35 - 65 % t r rise time 0.6 to 2.6 v -- 5ns t f fall time 2.6 to 0.6 v -- 5ns data and control signal output timing x-port, related to xclk output (for xpck[1:0]83h[5:4] = 00 is default); note 2 c l output load capacitance 15 - 50 pf t ohd;dat output data hold time c l =15pf - 14 - ns t pd propagation delay from positive edge of xclk output c l =15pf - 24 - ns t f fall time -- ns control signal output timing rt port, related to llc output c l output load capacitance 15 - 50 pf t ohd;dat output hold time c l =15pf - 14 - ns t pd propagation delay from positive edge of llc output c l =15pf - 24 - ns t f fall time -- ns iclk output timing c l output load capacitance 15 - 50 pf t cy cycle time 31 - 45 ns d duty factors for t iclkh /t iclkl 35 - 65 % t r rise time 0.6 to 2.6 v -- 5ns symbol parameter conditions min. typ. max. unit
2000 mar 15 77 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h notes 1. the levels must be measured with load circuits; 1.2 k w at 3 v (ttl load); c l = 50 pf. 2. the effects of rise and fall times are included in the calculation of t ohd;dat and t pd . timings and levels refer to drawings and conditions illustrated in fig.39. 3. the crystal oscillator drive level is typical 0.28 mw. t f fall time 2.6 to 0.6 v -- 5ns data and control signal output timing i-port, related to iclk output (for ipck[1:0]87h[5:4] = 00 is default) c l output load capacitance at all outputs 15 - 50 pf t ohd;dat output data hold time c l =15pf - 12 - ns t o(d) output delay time c l =15pf - 22 - ns t dis port disable time to 3-state c l =25pf -- ns t en port enable time from 3-state c l =25pf -- ns iclk input timing t cy cycle time 31 - 100 ns t l , t h low and high times -- ns t r rise time -- ns data and control signal output timing i-port, related to iclk input (for icks[1:0]80h[1:0] = 11) c l output load capacitance at all outputs - pf t ohd;dat output data hold time c l =15pf - - ns t o(d) output delay time c l =15pf - - ns t dis port disable time to 3-state c l =25pf -- ns t en port enable time from 3-state c l =25pf -- ns symbol parameter conditions min. typ. max. unit
2000 mar 15 78 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h handbook, full pagewidth mhb569 t xclkh t r t r t f t hd;dat t su;dat t su;dat t hd;dat t cy t x(i)clkh t x(i)clkl t f clock input xclk data and control inputs (x port) data and control outputs x port, i port clock outputs xclk, iclk and iclk-input input xdq 2.4 v 1.5 v 0.6 v - 2.6 v - 1.5 v - 0.6 v 2.0 v 0.8 v t ohd;dat t o(d) - 2.4 v - 0.6 v 2.0 v 0.8 v not valid fig.39 data input/output timing diagram (x-port, rt port and i-port).
2000 mar 15 79 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 14 application information handbook, full pagewidth c9 100 nf c24 10 m f 3.3 v (d) 3.3 v (d) c7 100 nf c2 100 nf c3 100 nf c4 100 nf c5 100 nf c6 100 nf c12 100 nf c10 100 nf c11 100 nf c13 100 nf c8 100 nf c1 100 nf c23 10 m f 3.3 v (a) r19 open dgnd agnd agnd agnd agnd agnd ai11 ai12 ce ai21 ai22 ai23 ai24 r23 3.3 k w 0 w r6 18 w r7 56 w r8 56 w r9 56 w r10 56 w r11 56 w r1 r12 56 w r14 3.3 k w r24 0 w c26 19 47 nf c18 18 47 nf c25 13 47 nf c16 16 47 nf c15 14 47 nf c14 12 47 nf c17 10 47 nf c19 20 ai1d ai12 ai2d ai21 ai22 ai23 ai24 ai11 47 nf r16 18 w r4 18 w r2 18 w r3 18 w r5 18 w dgnd dgnd tp1 tp5 tp6 xcon [ 7:0 ] xpd [ 7:0 ] llc rts0 rts1 rtco reson tp7 tp4 tp2 tp3 l1 10 m h y1 dgnd 24.576 mhz c20 10 pf 1 nf c22 c21 10 pf imcon [ 7:0 ] ipdl [ 7:0 ] hpdl [ 7:0 ] bst2 bst [ 2:0 ] tdi tdo v dd(3.3) 3.3 v (d) 3.3 v (a) l2 2.2 m h l3 2.2 m h v dda(3.3) aout sda scl r18 0 w r21 open r22 open r15 3.3 k w 0 w r17 aclk 3.3 v (d) dgnd r20 open r13 open strapping clock frequency strapping i 2 c-bus slave address place 0 w if bst is not used amclk asclk alrclk amxclk xtalo xtali 37 39 40 41 6 7 92 xrh 91 xrv 96 xrdy 95 xdq 94 xclk 80 xtri 4 xtout xcon0 xcon1 xcon2 xcon3 xcon4 xcon5 xcon6 81 xpd7 82 xpd6 84 xpd5 85 xpd4 86 xpd3 87 xpd2 89 xpd1 90 xpd0 xpd7 xpd6 xpd5 xpd4 xpd3 xpd2 xpd1 xpd0 36 rtco 35 rts1 34 rts0 44 test0 73 test1 74 test2 28 llc 29 llc2 30 res 26 v ssde1 100 v ssde2 76 v ssde3 50 v ssde4 5 v ssx 88 v ssdi3 63 v ssdi2 38 v ssdi1 27 ce 24 v ssa0 15 v ssa1 9 v ssa2 21 agnd igph itrdy iclk idq itri igp0 igp1 igpv imcon0 imcon7 imcon6 imcon5 imcon4 imcon3 imcon2 imcon1 53 42 62 61 60 59 57 56 55 ipd7 ipd6 ipd5 ipd4 ipd3 ipd2 ipd1 ipd0 ipd6 ipd5 ipd4 ipd3 ipd2 ipd1 ipd0 ipd7 54 45 46 47 48 49 52 98 99 97 3 2 tck tms trst tdi tdo bst0 bst1 bst2 23 17 11 25 75 51 1 334358688393 SAA7114h 8 v ddx v ddde1 v dddi1 v dddi2 v dddi3 v dddi4 v dddi5 v dddi6 v dda0 v dda1 v dda2 v ddde2 v ddde4 v ddde3 72 71 70 69 67 66 65 64 77 31 32 22 hpd5 hpd6 hpd7 test3 scl sda aout 78 79 test4 test5 hpd0 hpd1 hpd2 hpd3 hpd4 hpd5 hpd6 hpd7 hpd0 hpd1 hpd2 hpd3 hpd4 mhb527 fig.40 application example with 24.576 mhz crystal.
2000 mar 15 80 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15 i 2 c-bus description the SAA7114h supports the fast mode i 2 c-bus specification extension (data rate up to 400 kbits/s). 15.1 i 2 c-bus format handbook, full pagewidth xtal xtali 6 7 mhb558 xtal l 10 m h 20% c 10 pf c 10 pf c 1 nf quartz (3rd harmonic) 24.576 mhz xtali 6 7 SAA7114h SAA7114h fig.41 oscillator application. a. with quartz crystal. b. with external clock. handbook, full pagewidth ack-s ack-s data slave address w data transferred (n bytes + acknowledge) mhb339 p s ack-s subaddress a. write procedure. b. read procedure (combined). handbook, full pagewidth ack-s ack-m slave address r mhb340 p sr ack-s ack-s data subaddress slave address w s data transferred (n bytes + acknowledge) fig.42 i 2 c-bus format.
2000 mar 15 81 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 34 description of i 2 c-bus format note 1. if pin rtco strapped to ground via a 3.3 k w resistor. table 35 subaddress description and access code description s start condition sr repeated start condition slave address w 0100 0010 (= 42h, default) or 0100 0000 (= 40h; note 1) slave address r 0100 0011 (= 43h, default) or 0100 0001 (= 41h; note 1) ack-s acknowledge generated by the slave ack-m acknowledge generated by the master subaddress subaddress byte; see tables 35 and 36 data data byte; see table 36; if more than one byte data is transmitted the subaddress pointer is automatically incremented p stop condition x read/write control bit (lsb slave address); x = 0, order to write (the circuit is slave receiver); x = 1, order to read (the circuit is slave transmitter) subaddress description access (read/write) 00h chip version read only f0h to ffh reserved - video decoder: 01h to 2fh 01h to 05h front-end part read and write 06h to 19h decoder part read and write 1ah to 1eh reserved - 1fh video decoder status byte read only 20h to 2fh reserved - audio clock generation: 30h to 3fh 30h to 3ah audio clock generator read and write 3bh to 3fh reserved - general purpose vbi-data slicer: 40h to 7fh 40h to 60h vbi-data slicer read and write 61h to 62h vbi-data slicer status read only 64h to 7fh reserved - x-port, i-port and the scaler: 80h to efh 80h to 8fh task independent global settings read and write 90h to bfh task a de?nition read and write c0h to efh task b de?nition read and write
2000 mar 15 82 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 36 i 2 c-bus receiver/transmitter overview register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0 chip version: register 00h chip version (read only) 00 id07 id06 id05 id04 ---- video decoder: registers 01h to 2fh f ront - end part : registers 01h to 05h horizontal increment delay 01 (1) (1) (1) (1) idel3 idel2 idel1 idel0 analog input control 1 02 fuse1 fuse0 gudl1 gudl0 mode3 mode2 mode1 mode0 analog input control 2 03 (1) hlnrs vbsl wpoff holdg gafix gai28 gai18 analog input control 3 04 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 analog input control 4 05 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 d ecoder part : registers 06h to 2fh horizontal sync start 06 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 horizontal sync stop 07 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 sync control 08 aufd fsel foet htc1 htc0 hpll vnoi1 vnoi0 luminance control 09 byps ycomb ldel lubw lufi3 lufi2 lufi1 lufi0 luminance brightness control 0a dbri7 dbri6 dbri5 dbri4 dbri3 dbri2 dbri1 dbri0 luminance contrast control 0b dcon7 dcon6 dcon5 dcon4 dcon3 dcon2 dcon1 dcon0 chrominance saturation control 0c dsat7 dsat6 dsat5 dsat4 dsat3 dsat2 dsat1 dsat0 chrominance hue control 0d huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 chrominance control 1 0e cdto cstd2 cstd1 cstd0 dcvf fctc (1) ccomb chrominance gain control 0f acgc cgain6 cgain5 cgain4 cgain3 cgain2 cgain1 cgain0 chrominance control 2 10 offu1 offu0 offv1 offv0 chbw lcbw2 lcbw1 lcbw0 mode/delay control 11 colo rtp1 hdel1 hdel0 rtp0 ydel2 ydel1 ydel0 rt signal control 12 rtse13 rtse12 rtse11 rtse10 rtse03 rtse02 rtse01 rtse00 rt/x-port output control 13 rtce xrhs xrvs1 xrvs0 hlsel ofts2 ofts1 ofts0 analog/adc/compatibility control 14 cm99 uptcv aosl1 aosl0 xtoute oldsb apck1 apck0 vgate start, fid change 15 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 vgate stop 16 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 miscellaneous/vgate msbs 17 llce llc2e (1) (1) (1) vgps vsto8 vsta8
2000 mar 15 83 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... raw data gain control 18 rawg7 rawg6 rawg5 rawg4 rawg3 rawg2 rawg1 rawg0 raw data offset control 19 rawo7 rawo6 rawo5 rawo4 rawo3 rawo2 rawo1 rawo0 reserved 1a to 1e (1) (1) (1) (1) (1) (1) (1) (1) status byte video decoder (read only, oldsb = 0) 1f intl hlvln fidt glimt glimb wipa copro rdcap status byte video decoder (read only, oldsb = 1) 1f intl hlck fidt glimt glimb wipa sltca code reserved 20 to 2f (1) (1) (1) (1) (1) (1) (1) (1) audio clock generator part: registers 30h to 3fh audio master clock cycles per ?eld 30 acpf7 acpf6 acpf5 acpf4 acpf3 acpf2 acpf1 acpf0 31 acpf15 acpf14 acpf13 acpf12 acpf11 acpf10 acpf9 acpf8 32 (1) (1) (1) (1) (1) (1) acpf17 acpf16 reserved 33 (1) (1) (1) (1) (1) (1) (1) (1) audio master clock nominal increment 34 acni7 acni6 acni5 acni4 acni3 acni2 acni1 acni0 35 acni15 acni14 acni13 acni12 acni11 acni10 acni9 acni8 36 (1) (1) acni21 acni20 acni19 acni18 acni17 acni16 reserved 37 (1) (1) (1) (1) (1) (1) (1) (1) clock ratio amclk to asclk 38 (1) (1) sdiv5 sdiv4 sdiv3 sdiv2 sdiv1 sdiv0 clock ratio asclk to alrclk 39 (1) (1) lrdiv5 lrdiv4 lrdiv3 lrdiv2 lrdiv1 lrdiv0 audio clock control 3a (1) (1) (1) (1) apll amvr lrph scph reserved 3b to 3f (1) (1) (1) (1) (1) (1) (1) (1) general purpose vbi-data slicer part: registers 40h to 7fh slicer control 1 40 (1) ham_n fce hunt_n (1) (1) (1) (1) lcr2 to lcr24 (n = 2 to 24) 41 to 57 lcrn_7 lcrn_6 lcrn_5 lcrn_4 lcrn_3 lcrn_2 lcrn_1 lcrn_0 programmable framing code 58 fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 horizontal offset for slicer 59 hoff7 hoff6 hoff5 hoff4 hoff3 hoff2 hoff1 hoff0 vertical offset for slicer 5a voff7 voff6 voff5 voff4 voff3 voff2 voff1 voff0 field offset and msbs for horizontal and vertical offset 5b foff recode (1) voff8 (1) hoff10 hoff9 hoff8 reserved (for testing) 5c (1) (1) (1) (1) (1) (1) (1) (1) register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2000 mar 15 84 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... header and data identi?cation (did) code control 5d fvref (1) did5 did4 did3 did2 did1 did0 sliced data identi?cation (sdid) code 5e (1) (1) sdid5 sdid4 sdid3 sdid2 sdid1 sdid0 reserved 5f (1) (1) (1) (1) (1) (1) (1) (1) slicer status byte 0 (read only) 60 - fc8v fc7v vpsv ppv ccv -- slicer status byte 1 (read only) 61 -- f21_n ln8 ln7 ln6 ln5 ln4 slicer status byte 2 (read only) 62 ln3 ln2 ln1 ln0 dt3 dt2 dt1 dt0 reserved 63 to 7f (1) (1) (1) (1) (1) (1) (1) (1) x-port, i-port and the scaler part: registers 80h to efh t ask independent global settings : 80h to 8fh global control 1 80 (1) smod teb tea icks3 icks2 icks1 icks0 reserved 81 and 82 (1) (1) (1) (1) (1) (1) (1) (1) x-port i/o enable and output clock phase control 83 (1) (1) xpck1 xpck0 (1) xrqt xpe1 xpe0 i-port signal de?nitions 84 idg01 idg00 idg11 idg10 idv1 idv0 idh1 idh0 i-port signal polarities 85 iswp1 iswp0 illv ig0p ig1p irvp irhp idqp i-port fifo ?ag control and arbitration 86 vitx1 vitx0 idg02 idg12 ffl1 ffl0 fel1 fel0 i-port i/o enable, output clock and gated clock phase control 87 ipck3 ipck2 ipck1 ipck0 (1) (1) ipe1 ipe0 power save control 88 ch4en ch2en swrst dprog slm3 (1) slm1 slm0 reserved 89 to 8e (1) (1) (1) (1) (1) (1) (1) (1) status information scaler part 8f xtri itri ffil ffov prdon err_of fidsci fidsco t ask a definition : registers 90h to bfh basic settings and acquisition window de?nition task handling control 90 conlh ofidc fskp2 fskp1 fskp0 rptsk strc1 strc0 x-port formats and con?guration 91 conlv hldfv scsrc1 scsrc0 scrqe fsc2 fsc1 fsc0 x-port input reference signal de?nition 92 xfdv xfdh xdv1 xdv0 xcode xdh xdq xcks register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2000 mar 15 85 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... i-port format and con?guration 93 icode i8_16 fysk foi1 foi0 fsi2 fsi1 fsi0 horizontal input window start 94 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 95 (1) (1) (1) (1) xo11 xo10 xo9 xo8 horizontal input window length 96 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 97 (1) (1) (1) (1) xs11 xs10 xs9 xs8 vertical input window start 98 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 99 (1) (1) (1) (1) yo11 yo10 yo9 yo8 vertical input window length 9a ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 9b (1) (1) (1) (1) ys11 ys10 ys9 ys8 horizontal output window length 9c xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 9d (1) (1) (1) (1) xd11 xd10 xd9 xd8 vertical output window length 9e yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 9f (1) (1) (1) (1) yd11 yd10 yd9 yd8 fir ?ltering and prescaling horizontal prescaling a0 (1) (1) xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 accumulation length a1 (1) (1) xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 prescaler dc gain and fir pre?lter control a2 pfuv1 pfuv0 pfy1 pfy0 xc2_1 xdcg2 xdcg1 xdcg0 reserved a3 (1) (1) (1) (1) (1) (1) (1) (1) luminance brightness setting a4 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast setting a5 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chrominance saturation setting a6 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 reserved a7 (1) (1) (1) (1) (1) (1) (1) (1) horizontal phase scaling horizontal luminance scaling increment a8 xscy7 xscy6 xscy5 xscy4 xscy3 xscy2 xscy1 xscy0 a9 (1) (1) (1) xscy12 xscy11 xscy10 xscy9 xscy8 horizontal luminance phase offset aa xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 reserved ab (1) (1) (1) (1) (1) (1) (1) (1) register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2000 mar 15 86 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... horizontal chrominance scaling increment ac xscc7 xscc6 xscc5 xscc4 xscc3 xscc2 xscc1 xscc0 ad (1) (1) (1) xscc12 xscc11 xscc10 xscc9 xscc8 horizontal chrominance phase offset ae xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 reserved af (1) (1) (1) (1) (1) (1) (1) (1) vertical scaling vertical luminance scaling increment b0 yscy7 yscy6 yscy5 yscy4 yscy3 yscy2 yscy1 yscy0 b1 yscy15 yscy14 yscy13 yscy12 yscy11 yscy10 yscy9 yscy8 vertical chrominance scaling increment b2 yscc7 yscc6 yscc5 yscc4 yscc3 yscc2 yscc1 yscc0 b3 yscc15 yscc14 yscc13 yscc12 yscc11 yscc10 yscc9 yscc8 vertical scaling mode control b4 (1) (1) (1) ymir (1) (1) (1) ymode reserved b5 to b7 (1) (1) (1) (1) (1) (1) (1) (1) vertical chrominance phase offset 00 b8 ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 vertical chrominance phase offset 01 b9 ypc17 ypc16 ypc15 ypc14 ypc13 ypc12 ypc11 ypc10 vertical chrominance phase offset 10 ba ypc27 ypc26 ypc25 ypc24 ypc23 ypc22 ypc21 ypc20 vertical chrominance phase offset 11 bb ypc37 ypc36 ypc35 ypc34 ypc33 ypc32 ypc31 ypc30 vertical luminance phase offset 00 bc ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 vertical luminance phase offset 01 bd ypy17 ypy16 ypy15 ypy14 ypy13 ypy12 ypy11 ypy10 vertical luminance phase offset 10 be ypy27 ypy26 ypy25 ypy24 ypy23 ypy22 ypy21 ypy20 vertical luminance phase offset 11 bf ypy37 ypy36 ypy35 ypy34 ypy33 ypy32 ypy31 ypy30 t ask b definition registers c0h to efh basic settings and acquisition window de?nition task handling control c0 conlh ofidc fskp2 fskp1 fskp0 rptsk strc1 strc0 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2000 mar 15 87 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... x-port formats and con?guration c1 conlv hldfv scsrc1 scsrc0 scrqe fsc2 fsc1 fsc0 input reference signal de?nition c2 xfdv xfdh xdv1 xdv0 xcode xdh xdq xcks i-port format and con?guration c3 icode i8_16 fysk foi1 foi0 fsi2 fsi1 fsi0 horizontal input window start c4 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 c5 (1) (1) (1) (1) xo11 xo10 xo9 xo8 horizontal input window length c6 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 c7 (1) (1) (1) (1) xs11 xs10 xs9 xs8 vertical input window start c8 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 c9 (1) (1) (1) (1) yo11 yo10 yo9 yo8 vertical input window length ca ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 cb (1) (1) (1) (1) ys11 ys10 ys9 ys8 horizontal output window length cc xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 cd (1) (1) (1) (1) xd11 xd10 xd9 xd8 vertical output window length ce yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 cf (1) (1) (1) (1) yd11 yd10 yd9 yd8 fir ?ltering and prescaling horizontal prescaling d0 (1) (1) xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 accumulation length d1 (1) (1) xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 prescaler dc gain and fir pre?lter control d2 pfuv1 pfuv0 pfy1 pfy0 xc2_1 xdcg2 xdcg1 xdcg0 reserved d3 (1) (1) (1) (1) (1) (1) (1) (1) luminance brightness setting d4 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast setting d5 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chrominance saturation setting d6 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 reserved d7 (1) (1) (1) (1) (1) (1) (1) (1) horizontal phase scaling horizontal luminance scaling increment d8 xscy7 xscy6 xscy5 xscy4 xscy3 xscy2 xscy1 xscy0 d9 (1) (1) (1) xscy12 xscy11 xscy10 xscy9 xscy8 horizontal luminance phase offset da xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2000 mar 15 88 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. all unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. reserved db (1) (1) (1) (1) (1) (1) (1) (1) horizontal chrominance scaling increment dc xscc7 xscc6 xscc5 xscc4 xscc3 xscc2 xscc1 xscc0 dd (1) (1) (1) xscc12 xscc11 xscc10 xscc9 xscc8 horizontal chrominance phase offset de xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 reserved df (1) (1) (1) (1) (1) (1) (1) (1) vertical scaling vertical luminance scaling increment e0 yscy7 yscy6 yscy5 yscy4 yscy3 yscy2 yscy1 yscy0 e1 yscy15 yscy14 yscy13 yscy12 yscy11 yscy10 yscy9 yscy8 vertical chrominance scaling increment e2 yscc7 yscc6 yscc5 yscc4 yscc3 yscc2 yscc1 yscc0 e3 yscc15 yscc14 yscc13 yscc12 yscc11 yscc10 yscc9 yscc8 vertical scaling mode control e4 (1) (1) (1) ymir (1) (1) (1) ymode reserved e5 to e7 (1) (1) (1) (1) (1) (1) (1) (1) vertical chrominance phase offset 00 e8 ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 vertical chrominance phase offset 01 e9 ypc17 ypc16 ypc15 ypc14 ypc13 ypc12 ypc11 ypc10 vertical chrominance phase offset 10 ea ypc27 ypc26 ypc25 ypc24 ypc23 ypc22 ypc21 ypc20 vertical chrominance phase offset 11 eb ypc37 ypc36 ypc35 ypc34 ypc33 ypc32 ypc31 ypc30 vertical luminance phase offset 00 ec ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 vertical luminance phase offset 01 ed ypy17 ypy16 ypy15 ypy14 ypy13 ypy12 ypy11 ypy10 vertical luminance phase offset 10 ee ypy27 ypy26 ypy25 ypy24 ypy23 ypy22 ypy21 ypy20 vertical luminance phase offset 11 ef ypy37 ypy36 ypy35 ypy34 ypy33 ypy32 ypy31 ypy30 register function sub addr. (hex) d7 d6 d5 d4 d3 d2 d1 d0
2000 mar 15 89 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2 i 2 c-bus details 15.2.1 s ubaddress 00h table 37 chip version (cv) identi?cation; 00h[7:4]; read only register 15.2.2 s ubaddress 01h the programming of the horizontal increment delay is used to match internal processing delays to the delay of the adc. use recommended position only. table 38 horizontal increment delay; 01h[3:0] 15.2.3 s ubaddress 02h table 39 analog input control 1 (aico1); 02h[7:0] function logic levels id07 id06 id05 id04 chip version (cv) cv0 cv1 cv2 cv3 function idel3 idel2 idel1 idel0 no update 1 1 1 1 minimum delay 1 1 1 0 recommended position 1 0 0 0 maximum delay 0 0 0 0 bit description symbol value function d[7:6] analog function select (see fig.6) fuse[1:0] 00 ampli?er plus anti-alias ?lter bypassed 01 10 ampli?er active 11 ampli?er plus anti-alias ?lter active d[5:4] update hysteresis for 9-bit gain (see fig.7) gudl[1:0] 00 off 01 1 lsb 10 2 lsb 11 3 lsb
2000 mar 15 90 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h note 1. to take full advantage of the y/c-modes 6 to 9 the i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). d[3:0] mode selection mode[3:0] 0000 mode 0 : cvbs (automatic gain) from ai11 (pin 20); see fig. 43 0001 mode 1 : cvbs (automatic gain) from ai12 (pin 18); see fig. 44 0010 mode 2 : cvbs (automatic gain) from ai21 (pin 16); see fig. 45 0011 mode 3 : cvbs (automatic gain) from ai22 (pin 14); see fig. 46 0100 mode 4 : cvbs (automatic gain) from ai23 (pin 12); see fig. 47 0101 mode 5 : cvbs (automatic gain) from ai24 (pin 10); see fig. 48 0110 mode 6 : y (automatic gain) from ai11 (pin 20) + c (gain adjustable via gai28 to gai20) from ai21 (pin 16); note 1; see fig. 49 0111 mode 7 : y (automatic gain) from ai12 (pin 18) + c (gain adjustable via gai28 to gai20) from ai22 (pin 14); note 1; see fig. 50 1000 mode 8 : y (automatic gain) from ai11 (pin 20) + c (gain adapted to y gain) from ai21 (pin 16); note 1; see fig. 51 1001 mode 9 : y (automatic gain) from ai12 (pin 18) + c (gain adapted to y gain) from ai22 (pin 14); note 1; see fig. 52 1111 modes 10 to 15 : reserved bit description symbol value function fig.43 mode 0; cvbs (automatic gain). handbook, halfpage mhb559 ai22 ai21 ai12 ai11 ad2 ad1 chroma luma ai24 ai23 fig.44 mode 1; cvbs (automatic gain). handbook, halfpage mhb560 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 fig.45 mode 2; cvbs (automatic gain). handbook, halfpage mhb561 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 fig.46 mode 3; cvbs (automatic gain). handbook, halfpage mhb562 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23
2000 mar 15 91 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h fig.47 mode 4; cvbs (automatic gain). handbook, halfpage mhb563 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 fig.48 mode 5; cvbs (automatic gain). handbook, halfpage mhb564 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 fig.49 mode 6; y + c (gain channel 2 adjusted via gai2). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). handbook, halfpage mhb565 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 fig.50 mode 7; y + c (gain channel 2 adjusted via gai2). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). handbook, halfpage mhb566 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 fig.51 mode 8; y + c (gain channel 2 adapted to y gain). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). handbook, halfpage mhb567 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23 fig.52 mode 9; y + c (gain channel 2 adapted to y gain). i 2 c-bus bit byps (subaddress 09h, bit 7) should be set to logic 1 (full luminance bandwidth). handbook, halfpage mhb568 ai12 ai11 ad2 ad1 chroma luma ai22 ai21 ai24 ai23
2000 mar 15 92 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.4 s ubaddress 03h table 40 analog input control 2 (aico2); 03h[6:0] 15.2.5 s ubaddress 04h table 41 analog input control 3 (aico3): static gain control channel 1; 03h[0] and 04h[7:0] 15.2.6 s ubaddress 05h table 42 analog input control 4 (aico4); static gain control channel 2; 03h[1] and 05h[7:0] bit description symbol value function d6 hl not reference select hlnrs 0 normal clamping if decoder is in unlocked state 1 reference select if decoder is in unlocked state d5 agc hold during vertical blanking period vbsl 0 short vertical blanking (agc disabled during equalization and serration pulses) 1 long vertical blanking (agc disabled from start of pre-equalization pulses until start of active video (line 22 for 60 hz, line 24 for 50 hz) d4 white peak off wpoff 0 white peak control active 1 white peak off d3 automatic gain control integration holdg 0 agc active 1 agc integration hold (freeze) d2 gain control ?x gafix 0 automatic gain controlled by mode3 to mode0 1 gain is user programmable via gai[17:10] and gai[27:20] d1 static gain control channel 2 sign bit gai28 see table 42 d0 static gain control channel 1 sign bit gai18 see table 41 decimal value gain (db) sign bit 03h[0] control bits d7 to d0 gai18 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 0... - 3 0 00000000 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1 decimal value gain (db) sign bit 03h[1] control bits d7 to d0 gai28 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 0... - 3 0 00000000 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1
2000 mar 15 93 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.7 s ubaddress 06h table 43 horizontal sync start; 06h[7:0] 15.2.8 s ubaddress 07h table 44 horizontal sync stop; 07h[7:0] delay time (step size = 8/llc) control bits d7 to d0 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 - 128... - 109 (50 hz) forbidden (outside available central counter range) - 128... - 108 (60 hz) - 108 (50 hz)... 1 0 0 1 0 1 0 0 - 107 (60 hz)... 1 0 0 1 0 1 0 1 ...108 (50 hz) 0 1 1 0 1 1 0 0 ...107 (60 hz) 0 1 1 0 1 0 1 1 109...127 (50 hz) forbidden (outside available central counter range) 108...127 (60 hz) delay time (step size = 8/llc) control bits d7 to d0 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 - 128... - 109 (50 hz) forbidden (outside available central counter range) - 128... - 108 (60 hz) - 108 (50 hz)... 1 0 0 1 0 1 0 0 - 107 (60 hz)... 1 0 0 1 0 1 0 1 ...108 (50 hz) 0 1 1 0 1 1 0 0 ...107 (60 hz) 0 1 1 0 1 0 1 1 109...127 (50 hz) forbidden (outside available central counter range) 108...127 (60 hz)
2000 mar 15 94 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.9 s ubaddress 08h table 45 sync control; 08h[7:0] bit description symbol value function d7 automatic ?eld detection aufd 0 ?eld state directly controlled via fsel 1 automatic ?eld detection; recommended setting d6 ?eld selection fsel 0 50 hz, 625 lines 1 60 hz, 525 lines d5 forced odd/even toggle foet 0 odd/even signal toggles only with interlaced source 1 odd/even signal toggles ?eldwise even if source is non-interlaced d[4:3] horizontal time constant selection htc[1:0] 00 tv mode, recommended for poor quality tv signals only; do not use for new applications 01 vtr mode, recommended if a de?ection control circuit is directly connected to the SAA7114h 10 reserved 11 fast locking mode; recommended setting d2 horizontal pll hpll 0 pll closed 1 pll open; horizontal frequency ?xed d[1:0] vertical noise reduction vnoi[1:0] 00 normal mode; recommended setting 01 fast mode, applicable for stable sources only; automatic ?eld detection (aufd) must be disabled 10 free running mode 11 vertical noise reduction bypassed
2000 mar 15 95 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.10 s ubaddress 09h table 46 luminance control; 09h[7:0] 15.2.11 s ubaddress 0ah table 47 luminance brightness control: decoder part; 0ah[7:0] bit description symbol value function d7 chrominance trap/comb ?lter bypass byps 0 chrominance trap or luminance comb ?lter active; default for cvbs mode 1 chrominance trap or luminance comb ?lter bypassed; default for s-video mode d6 adaptive luminance comb ?lter ycomb 0 disabled (= chrominance trap enabled, if byps = 0) 1 active, if byps = 0 d5 processing delay in non comb ?lter mode ldel 0 processing delay is equal to internal pipelining delay 1 one (ntsc standards) or two (pal standards) video lines additional processing delay d4 remodulation bandwidth for luminance; see figs 12 to 15 lubw 0 small remodulation bandwidth (narrow chroma notch t higher luminance bandwidth) 1 large remodulation bandwidth (wider chroma notch t smaller luminance bandwidth) d[3:0] sharpness control, luminance ?lter characteristic; see fig.16 lufi[3:0] 0001 resolution enhancement ?lter 8.0 db at 4.1 mhz 0010 resolution enhancement ?lter 6.8 db at 4.1 mhz 0011 resolution enhancement ?lter 5.1 db at 4.1 mhz 0100 resolution enhancement ?lter 4.1 db at 4.1 mhz 0101 resolution enhancement ?lter 3.0 db at 4.1 mhz 0110 resolution enhancement ?lter 2.3 db at 4.1 mhz 0111 resolution enhancement ?lter 1.6 db at 4.1 mhz 0000 plain 1000 low-pass ?lter 2 db at 4.1 mhz 1001 low-pass ?lter 3 db at 4.1 mhz 1010 low-pass ?lter 3 db at 3.3 mhz; 4 db at 4.1 mhz 1011 low-pass ?lter 3 db at 2.6 mhz; 8 db at 4.1 mhz 1100 low-pass ?lter 3 db at 2.4 mhz; 14 db at 4.1 mhz 1101 low-pass ?lter 3 db at 2.2 mhz; notch at 3.4 mhz 1110 low-pass ?lter 3 db at 1.9 mhz; notch at 3.0 mhz 1111 low-pass ?lter 3 db at 1.7 mhz; notch at 2.5 mhz offset control bits d7 to d0 dbri7 dbri6 dbri5 dbri4 dbri3 dbri2 dbri1 dbri0 255 (bright) 11111111 128 (itu level) 10000000 0 (dark) 00000000
2000 mar 15 96 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.12 s ubaddress 0bh table 48 luminance contrast control; decoder part; 0bh[7:0] 15.2.13 s ubaddress 0ch table 49 chrominance saturation control: decoder part; 0ch[7:0] 15.2.14 s ubaddress 0dh table 50 chrominance hue control; 0dh[7:0] gain control bits d7 to d0 dcon7 dcon6 dcon5 dcon4 dcon3 dcon2 dcon1 dcon0 1.984 (maximum) 01111111 1.063 (itu level) 01000100 1.0 01000000 0 (luminance off) 00000000 - 1 (inverse luminance) 11000000 - 2 (inverse luminance) 10000000 gain control bits d7 to d0 dsat7 dsat6 dsat5 dsat4 dsat3 dsat2 dsat1 dsat0 1.984 (maximum) 01111111 1.0 (itu level) 01000000 0 (colour off) 00000000 - 1 (inverse chrominance) 11000000 - 2 (inverse chrominance) 10000000 hue phase (deg) control bits d7 to d0 huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 +178.6... 01111111 ...0... 00000000 ... - 180 10000000
2000 mar 15 97 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.15 s ubaddress 0eh table 51 chrominance control 1; 0eh[7:0] 15.2.16 s ubaddress 0fh table 52 chrominance gain control; 0fh[7:0] bit description symbol value function 50 hz/625 lines 60 hz/525 lines d7 clear dto cstdo 0 disabled 1 every time cdto is set, the internal subcarrier dto phase is reset to 0 and the rtco output generates a logic 0 at time slot 68 (see external document rtc functional description , available on request). so an identical subcarrier phase can be generated by an external device (e.g. an encoder). d[6:4] colour standard selection cstd[2:0] 000 pal bgdhi (4.43 mhz) ntsc m (3.58 mhz) 001 ntsc 4.43 (50 hz) pal 4.43 (60 hz) 010 combination-pal n (3.58 mhz) ntsc 4.43 (60 hz) 011 ntsc n (3.58 mhz) pal m (3.58 mhz) 100 reserved ntsc-japan (3.58 mhz) 101 secam reserved 110 reserved; do not use 111 reserved; do not use d3 disable chrominance vertical ?lter and pal phase error correction dcvf 0 chrominance vertical ?lter and pal phase error correction on (during active video lines) 1 chrominance vertical ?lter and pal phase error correction permanently off d2 fast colour time constant fctc 0 nominal time constant 1 fast time constant for special applications d0 adaptive chrominance comb ?lter ccomb 0 disabled 1 active bit description symbol value function d7 automatic chrominance gain control acgc 0 on 1 programmable gain via cgain6 to cgain0; need to be set for secam standard d[6:0] chrominance gain value (if acgc is set to logic 1) cgain[6:0] 000 0000 minimum gain (0.5) 010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5)
2000 mar 15 98 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.17 s ubaddress 10h table 53 chrominance control 2; 10h[7:0] 15.2.18 s ubaddress 11h table 54 mode/delay control; 11h[7:0] bit description symbol value function d[7:6] ?ne offset adjustment b-y component offu[1:0] 00 0 lsb 01 1 4 lsb 01 1 2 lsb 11 3 4 lsb d[5:4] ?ne offset adjustment r-y component offv[1:0] 00 0 lsb 01 1 4 lsb 10 1 2 lsb 11 3 4 lsb d3 chrominance bandwidth; see figs 10 and 11 chbw 0 small 1 wide d[2:0] combined luminance/chrominance bandwidth adjustment; see figs 10 to 16 lcbw[2:0] 000 smallest chrominance bandwidth/largest luminance bandwidth ... ... to ... 111 largest chrominance bandwidth/smallest luminance bandwidth bit description symbol value function d7 colour on colo 0 automatic colour killer enabled 1 colour forced on d6 polarity of rts1 output signal rtp1 0 non inverted 1 inverted d[5:4] ?ne position of hs (steps in 2/llc) hdel[1:0] 00 0 01 1 10 2 11 3 d3 polarity of rts0 output signal rtp0 0 non inverted 1 inverted d[2:0] luminance delay compensation (steps in 2/llc) ydel[2:0] 100 - 4... 000 ...0... 011 ...3
2000 mar 15 99 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.19 s ubaddress 12h table 55 rt signal control: rts0 output; 12h[3:0] the polarity of any signal on rts0 can be inverted via rtp0[11h[3]]. note 1. function of hl is selectable via hlsel[13h[3]]: a) hlsel = 0: hl is standard horizontal lock indicator. b) hlsel = 1: hl is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. vcrs). rts0 output rtse03 rtse02 rtse01 rtse00 3-state 0000 constant low 0 0 0 1 cref (13.5 mhz toggling pulse; see fig.23) 0 0 1 0 cref2 (6.75 mhz toggling pulse; see fig.23) 0 0 1 1 hl; horizontal lock indicator (note 1): 0 1 0 0 hl = 0: unlocked hl = 1: locked vl; vertical and horizontal lock: 0 1 0 1 vl = 0: unlocked vl = 1: locked dl, vertical and horizontal lock and colour detected: 0 1 1 0 dl = 0: unlocked dl = 1: locked reserved 0 1 1 1 href, horizontal reference signal; indicates 720 pixels valid data on the expansion port. the positive slope marks the beginning of a new active line. href is also generated during the vertical blanking interval (see fig.23). 1000 hs: 1001 programmable width in llc8 steps via hsb[7:0]06h[7:0] and hss[7:0]07h[7:0] fine position adjustment in llc2 steps via hdel[1:0]11h[5:4] (see fig.23) hq; href gated with vgate 1 0 1 0 reserved 1 0 1 1 v123; vertical sync (see vertical timing diagrams figs 21 and 22) 1 1 0 0 vgate; programmable via vsta[8:0]17h[0]15h[7:0], vsto[8:0]17h[1]16h[7:0] and vgps[17h[2]] 1101 lsbs of the 9-bit adcs 1 1 1 0 fid; position programmable via sta[8:0]17h[0]15h[7:0]; see vertical timing diagrams figs 21 and 22 1111
2000 mar 15 100 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 56 rt signal control: rts1 output; 12h[7:4] the polarity of any signal on rts1 can be inverted via rtp1[11h[6]]. note 1. function of hl is selectable via hlsel[13h[3]]: a) hlsel = 0: hl is standard horizontal lock indicator. b) hlsel = 1: hl is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. vcrs). rts1 output rtse13 rtse12 rtse11 rtse10 3-state 0000 constant low 0 0 0 1 cref (13.5 mhz toggling pulse; see fig.23) 0 0 1 0 cref2 (6.75 mhz toggling pulse; see fig.23) 0 0 1 1 hl; horizontal lock indicator (note 1): 0 1 0 0 hl = 0: unlocked hl = 1: locked vl; vertical and horizontal lock: 0 1 0 1 vl = 0: unlocked vl = 1: locked dl, vertical and horizontal lock and colour detected: 0 1 1 0 dl = 0: unlocked dl = 1: locked reserved 0 1 1 1 href, horizontal reference signal; indicates 720 pixels valid data on the expansion port. the positive slope marks the beginning of a new active line. href is also generated during the vertical blanking interval (see fig.23). 1000 hs: 1001 programmable width in llc8 steps via hsb[7:0]06h[7:0] and hss[7:0]07h[7:0] fine position adjustment in llc2 steps via hdel[1:0]11h[5:4] (see fig.23) hq; href gated with vgate 1 0 1 0 reserved 1 0 1 1 v123; vertical sync (see vertical timing diagrams figs 21 and 22) 1 1 0 0 vgate; programmable via vsta[8:0]17h[0]15h[7:0], vsto[8:0]17h[1]16h[7:0] and vgps[17h[2]] 1101 lsbs of the 9-bit adcs 1 1 1 0 fid; position programmable via sta[8:0]17h[0]15h[7:0]; see vertical timing diagrams figs 21 and 22 1111
2000 mar 15 101 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.20 s ubaddress 13h table 57 rt/x-port output control; 13h[7:0] bit description symbol value function d7 rtco output enable rtce 0 3-state 1 enabled d6 x-port xrh output selection xrhs 0 href (see fig.23) 1 hs: programmable width in llc8 steps via hsb[7:0]06h[7:0] and hss[7:0]07h[7:0] fine position adjustment in llc2 steps via hdel[1:0]11h[5:4] (see fig.23) d[5:4] x-port xrv output selection xrvs[1:0] 00 v123 (see figs 21 and 22) 01 itu 656 related ?eld id (see figs 21 and 22) 10 inverted v123 11 inverted itu 656 related ?eld id d3 horizontal lock indicator selection hlsel 0 copy of inverted hlck status bit (default) 1 fast horizontal lock indicator (for special applications only) d[2:0] xpd7 to xpd0 (port output format selection); see section 9.4 ofts[2:0] 000 itu 656 001 itu 656 like format with modi?ed ?eld blanking according to vgate position (programmable via vsta8 to vsta0, vsto8 to vsto0 and vgps, subaddresses 15h, 16h and 17h) 010 yuv4:2:2 8-bit format (no sav/eav codes inserted) 011 reserved 100 multiplexed ad2/ad1 bypass (bits 8 to 1) dependent on mode settings; if both adcs are selected ad2 is output at cref = 1 and ad1 is output at cref = 0 101 multiplexed ad2/ad1 bypass (bits 7 to 0) dependent on mode settings; if both adcs are selected ad2 is output at cref = 1 and ad1 is output at cref = 0 110 reserved 111 multiplexed adc msb/lsb bypass dependent on mode settings; only one adc should be selected at a time; adx8 to adx1 are outputs at cref = 1 and adx7 to adx0 are outputs at cref = 0
2000 mar 15 102 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.21 s ubaddress 14h table 58 analog/adc/compatibility control; 14h[7:0] bit description symbol value function d7 compatibility bit for saa7199 cm99 0 off (default) 1 on (to be set only if saa7199 is used for re-encoding in conjunction with rtco active ) d6 update time interval for agc value uptcv 0 horizontal update (once per line) 1 vertical update (once per ?eld) d[5:4] analog test select aosl[1:0] 00 aout connected to internal test point 1 01 aout connected to input ad1 10 aout connected to input ad2 11 aout connected to internal test point 2 d3 xtout output enable xtoute 0 pin 4 (xtout) 3-stated 1 pin 4 (xtout) enabled d2 decoder status byte selection; see table 64 oldsb 0 standard 1 backward compatibility to saa7112 d[1:0] adc sample clock phase delay apck[1:0] 00 application dependent 01 10 11
2000 mar 15 103 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 15.2.22 s ubaddress 15h table 59 vgate pulse; fid polarity change; 17h[0] and 15h[7:0] start of vgate pulse (low-to-high transition) and polarity change of fid pulse, vgps = 0; see figs 21 and 22. field frame line counting decimal value msb 17h[0] control bits d7 to d0 vsta8 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 50 hz 1st 1 312 1 00111000 2nd 314 1st 2 0... 0 0 0 0 0 0 0 0 0 2nd 315 1st 312 ...310 1 0 0 1 1 0 1 1 1 2nd 625 60 hz 1st 4 262 1 00000110 2nd 267 1st 5 0... 0 0 0 0 0 0 0 0 0 2nd 268 1st 265 ...260 1 0 0 0 0 0 1 0 1 2nd 3
2000 mar 15 104 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 15.2.23 s ubaddress 16h table 60 vgate stop; 17h[1] and 16h[7:0] stop of vgate pulse (high-to-low transition), vgps = 0; see figs 21 and 22. field frame line counting decimal value msb 17h[1] control bits d7 to d0 vsto8 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 50hz1st 1 312 1 00111000 2nd 314 1st 2 0... 0 00000000 2nd 315 1st 312 ...310 1 00110111 2nd 625 60hz1st 4 262 1 00000110 2nd 267 1st 5 0... 0 00000000 2nd 268 1st 265 ...260 1 00000101 2nd 3
2000 mar 15 105 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.24 s ubaddress 17h table 61 miscellaneous/vgate msbs; 17h[7:6] and 17h[2:0] 15.2.25 s ubaddress 18h table 62 raw data gain control; rawg[7:0]18h[7:0] see fig.18. 15.2.26 s ubaddress 19h table 63 raw data offset control; rawo[7:0]19h[7:0] see fig.18. bit description symbol value function d7 llc output enable llce 0 enable 1 3-state d6 llc2 output enable llc2e 0 enable 1 3-state d2 alternative vgate position vgps 0 vgate position according to tables 59 and 60 1 vgate occurs one line earlier during ?eld 2 d1 msb vgate stop vsto8 see table 60 d0 msb vgate start vsta8 see table 59 gain control bits d7 to d0 rawg7 rawg6 rawg5 rawg4 rawg3 rawg2 rawg1 rawg0 255 (double amplitude) 01111111 128 (nominal level) 01000000 0 (off) 00000000 offset control bits d7 to d0 rawo7 rawo6 rawo5 rawo4 rawo3 rawo2 rawo1 rawo0 - 128lsb 00000000 0lsb 10000000 +128 lsb 11111111
2000 mar 15 106 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.2.27 s ubaddress 1fh ( read only register ) table 64 status byte video decoder; 1fh[7:0] 15.3 programming register audio clock generation see equations in section 8.6 and examples in tables 21 and 22. 15.3.1 s ubaddresses 30h to 32h table 65 audio master clock (amclk) cycles per ?eld bit description i 2 c-bus control bit oldsb 14h[2] value function d7 status bit for interlace detection intl - 0 non-interlaced 1 interlaced d6 status bit for horizontal and vertical loop hlvln 0 0 both loops locked 1 unlocked status bit for locked horizontal frequency hlck 1 0 locked 1 unlocked d5 identi?cation bit for detected ?eld frequency fidt - 0 50 hz 1 60 hz d4 gain value for active luminance channel is limited; maximum (top) glimt - 0 not active 1 active d3 gain value for active luminance channel is limited; minimum (bottom) glimb - 0 not active 1 active d2 white peak loop is activated wipa - 0 not active 1 active d1 copy protected source detected according to macrovision version up to 7.01 copro 0 0 not active 1 active slow time constant active in wipa mode sltca 1 0 not active 1 active d0 ready for capture (all internal loops locked) rdcap 0 0 not active 1 active colour signal in accordance with selected standard has been detected code 1 0 not active 1 active subaddress control bits d7 to d0 30h acpf7 acpf6 acpf5 acpf4 acpf3 acpf2 acpf1 acpf0 31h acpf15 acpf14 acpf13 acpf12 acpf11 acpf10 acpf9 acpf8 32h ------ acpf17 acpf16
2000 mar 15 107 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.3.2 s ubaddresses 34h to 36h table 66 audio master clock (amclk) nominal increment 15.3.3 s ubaddress 38h table 67 clock ratio amclk (audio master clock) to asclk (serial bit clock) 15.3.4 s ubaddress 39h table 68 clock ratio asclk (serial bit clock) to alrclk (channel select clock) 15.3.5 s ubaddress 3ah table 69 audio clock control; 3ah[3:0] 15.4 programming register vbi-data slicer 15.4.1 s ubaddress 40h table 70 slicer control 1; 40h[6:4] subaddress control bits d7 to d0 34h acni7 acni6 acni5 acni4 acni3 acni2 acni1 acni0 35h acni15 acni14 acni13 acni12 acni11 acni10 acni9 acni8 36h -- acni21 acni20 acni19 acni18 acni17 acni16 subaddress control bits d7 to d0 38h -- sdiv5 sdiv4 sdiv3 sdiv2 sdiv1 sdiv0 subaddress control bits d7 to d0 39h -- lrdiv5 lrdiv4 lrdiv3 lrdiv2 lrdiv1 lrdiv0 bit description symbol value function d3 audio pll modes apll 0 pll active, amclk is ?eld-locked 1 pll open, amclk is free-running d2 audio master clock vertical reference amvr 0 vertical reference pulse is taken from internal decoder 1 vertical reference is taken from xrv input (expansion port) d1 alrclk phase lrph 0 alrclk edges triggered by falling edges of asclk 1 alrclk edges triggered by rising edges of asclk d0 asclk phase scph 0 asclk edges triggered by falling edges of amclk 1 asclk edges triggered by rising edges of amclk bit description symbol value function d6 hamming check ham_n 0 hamming check for 2 bytes after framing code, dependent on data type (default) 1 no hamming check d5 framing code error fce 0 one framing code error allowed 1 no framing code errors allowed d4 amplitude searching hunt_n 0 amplitude searching active (default) 1 amplitude searching stopped
2000 mar 15 108 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.4.2 s ubaddresses 41h to 57h table 71 line control register; lcr2 to lcr24 (41h to 57h) see sections 8.2 and 8.4. 15.4.3 s ubaddress 58h table 72 programmable framing code; slicer set 58h[7:0] according to tables 14 and 71. 15.4.4 s ubaddress 59h table 73 horizontal offset for slicer; slicer set 59h and 5bh name description framing code d[7:4] (41h to 57h) d[3:0] (41h to 57h) dt[3:0]62h[3:0] (field 1) dt[3:0]62h[3:0] (field 2) wst625 teletext eurowst, ccst 27h 0000 0000 cc625 european closed caption 001 0001 0001 vps video programming service 9951h 0010 0010 wss wide screen signalling bits 1e3c1fh 0011 0011 wst525 us teletext (wst) 27h 0100 0100 cc525 us closed caption (line 21) 001 0101 0101 test line video component signal, vbi region - 0110 0110 intercast raw data - 0111 0111 general text teletext programmable 1000 1000 vitc625 vitc/ebu time codes (europe) programmable 1001 1001 vitc/smpte time codes (usa) programmable 1010 1010 reserved reserved - 1011 1011 nabts us nabts - 1100 1100 japtext moji (japanese) programmable (a7h) 1101 1101 jfs japanese format switch (l20/22) programmable 1110 1110 active video video component signal, active video region (default) - 1111 1111 framing code for programmable data types control bits d7 to d0 default value fc[7:0] = 40h horizontal offset control bits d[2:0]5bh[2:0] control bits d[7:0]59h[7:0] recommended value hoff[10:8] = 3h hoff[7:0] = 47h
2000 mar 15 109 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.4.5 s ubaddress 5ah table 74 vertical offset for slicer; slicer set 5ah and 5bh 15.4.6 s ubaddress 5bh table 75 field offset, and msbs for horizontal and vertical offsets; slicer set 5bh[7:6] see sections 15.4.4 and 15.4.5 for hoff[10:8]5bh[2:0] and voff8[5bh[4]]. 15.4.7 s ubaddress 5dh table 76 header and data identi?cation (did; itu 656) code control; slicer set 5dh[7:0] 15.4.8 s ubaddress 5eh table 77 sliced data identi?cation (sdid) code; slicer set 5eh[5:0] vertical offset control bit d[4]5bh[4] control bits d[7:0]5ah[7:0] voff8 voff[7:0] minimum value 0 0 00h maximum value 312 1 38h value for 50 hz 625 lines input 0 03h value for 60 hz 525 lines input 0 06h bit description symbol value function d7 ?eld offset foff 0 no modi?cation of internal ?eld indicator (default for 50 hz 625 lines input sources) 1 invert ?eld indicator (default for 60 hz 525 lines input sources) d6 recode recode 0 let data unchanged (default) 1 convert 00h and ffh data bytes into 03h and fch bit description symbol value function d7 ?eld id and v-blank selection for text output (f and v reference selection) fvref 0 f and v output of slicer is lcr table dependent 1 f and v output is taken from decoder real time signals even_ccir and vblnk_ccir d[5:0] default; did[5:0] = 00h did[5:0] 00 0000 anc header framing ; see fig.30 and table 20 special cases of did programming 11 1110 did[5:0] = 3eh sav/eav framing, with fvref = 1 11 1111 did[5:0] = 3fh sav/eav framing, with fvref = 0 bit description symbol value function d[5:0] sdid codes sdid[5:0] 00h default
2000 mar 15 110 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.4.9 s ubaddress 60h ( read - only register ) table 78 slicer status byte 0; 60h[6:2] 15.4.10 s ubaddresses 61h and 62h ( read - only registers ) table 79 slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0] 15.5 programming register interfaces and scaler part 15.5.1 s ubaddress 80h table 80 global control 1; global set 80h[3:0] x = dont care. note 1. although the iclko i/o is independent of icks2 and icks3, this selection can only be used if icks2 = 1. bit description symbol value function d6 framing code valid fc8v 0 no framing code (0 error) in the last frame detected 1 framing code with 0 error detected d5 framing code valid fc7v 0 no framing code (1 error) in the last frame detected 1 framing code with 1 error detected d4 vps valid vpsv 0 no vps in the last frame 1 vps detected d3 palplus valid ppv 0 no palplus in the last frame 1 palplus detected d2 close caption valid ccv 0 no closed caption in the last frame 1 closed caption detected subaddress bit symbol description 61h d5 f21_n ?eld id as seen by the vbi slicer; for ?eld 1: d5 = 0 d[4:0] ln[8:4] line number 62h d[7:4] ln[3:0] d[3:0] dt[3:0] data type; according to table 14 i-port and scaler back-end clock selection control bits d3 to d0 icks3 icks2 icks1 icks0 iclk output and back-end clock is line-locked clock llc from decoder x x 0 0 iclk output and back-end clock is xclk from x-port x x 0 1 iclk output is llc and back-end clock is llc2 clock x x (1) 10 back-end clock is the iclk input x x 1 1 idq pin carries the data quali?er x 0 x x idq pin carries a gated back-end clock (idq and clk) x 1 x x idq generation only for valid data 0 x x x idq quali?es valid data inside the scaling region and all data outside the scaling region 1xxx
2000 mar 15 111 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 81 global control 1; global set 80h[6:4] swrst moved to subaddress 88h[5]; x = dont care. 15.5.2 s ubaddresses 83h to 87h table 82 x-port i/o enable and output clock phase control; global set 83h[5:4] table 83 x-port i/o enable and output clock phase control; global set 83h[2:0] x = dont care. task enable control control bits d6 to d4 smod teb tea task of register set a is disabled x x 0 task of register set a is enabled x x 1 task of register set b is disabled x 0 x task of register set b is enabled x 1 x the scaler window de?nes the f and v timing of the scaler output 0 x x vbi-data slicer de?nes the f and v timing of the scaler output 1 x x output clock phase control control bits d5 and d4 xpck1 xpck0 xclk default output phase, recommended value 00 xclk output inverted 0 1 xclk phase shifted by about 3 ns 1 0 xclk output inverted and shifted by about 3 ns 1 1 x-port i/o enable control bits d2 to d0 xrqt xpe1 xpe0 x-port output is disabled by software x 0 0 x-port output is enabled by software x 0 1 x-port output is enabled by pin xtri at logic 0 x 1 0 x-port output is enabled by pin xtri at logic 1 x 1 1 xrdy output signal is a/b task ?ag from event handler (a = 1) 0 x x xrdy output signal is ready signal from scaler path (xrdy = 1 means SAA7114h is ready to receive data) 1xx
2000 mar 15 112 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 84 i-port output signal de?nitions; global set 84h[3:0] x = dont care. table 85 i-port signal de?nitions; global set 84h[5:4] and 86h[4] i-port output signal definitions control bits d3 to d0 idv1 idv0 idh1 idh0 igph is a h-gate signal, framing the scaler output x x 0 0 igph is an extended h-gate (framing h-gate during scaler output and scaler input h-reference outside the scaler window) xx0 1 igph is a horizontal trigger pulse, on active going edge of h-gate x x 1 0 igph is a horizontal trigger pulse, on active going edge of extended h-gate x x 1 1 igpv is a v-gate signal, framing scaled output lines 0 0 x x igpv is the reference signal from scaler input 0 1 x x igpv is a vertical trigger pulse, derived from v-gate 1 0 x x igpv is a vertical trigger pulse derived from input v-reference 1 1 x x i-port signal definitions control bits 86h[4] 84h[5:4] idg12 idg11 idg10 igp1 is output ?eld id, as de?ned by ofidc[90h[6]] 0 0 0 igp1 is a/b task ?ag, as de?ned by conlh[90h[7]] 0 0 1 igp1 is sliced data ?ag, framing the sliced vbi-data at the i-port 0 1 0 igp1 is set to logic 0 (default polarity) 011 igp1 is the output fifo almost ?lled ?ag 1 0 0 igp1 is the output fifo over?ow ?ag 1 0 1 igp1 is the output fifo almost full ?ag, level to be programmed in subaddress 86h 110 igp1 is the output fifo almost empty ?ag, level to be programmed in subaddress 86h 111
2000 mar 15 113 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 86 i-port signal de?nitions; global set 84h[7:6] and 86h[5] table 87 i-port reference signal polarities; global set 85h[4:0] x = dont care. table 88 x-port signal de?nitions text slicer; global set 85h[7:5] x = dont care. i-port signal definitions control bits 86h[5] 84h[7:6] idg02 idg01 idg00 igp0 is output ?eld id, as de?ned by ofidc[90h[6]] 0 0 0 igp0 is a/b task ?ag, as de?ned by conlh[90h[7]] 0 0 1 igp0 is sliced data ?ag, framing the sliced vbi-data at the i-port 0 1 0 igp0 is set to logic 0 (default polarity) 011 igp0 is the output fifo almost ?lled ?ag 1 0 0 igp0 is the output fifo over?ow ?ag 1 0 1 igp0 is the output fifo almost full ?ag, level to be programmed in subaddress 86h 110 igp0 is the output fifo almost empty ?ag, level to be programmed in subaddress 86h 111 i-port reference signal polarities control bits d4 to d0 igp0p igp1p igvp ighp idqp idq at default polarity (1 = active) xxxx0 idq is inverted xxxx1 igph at default polarity (1 = active) x x x 0 x igph is inverted x x x 1 x igpv at default polarity (1 = active) x x 0 x x igpv is inverted x x 1 x x igp1 at default polarity x 0 x x x igp1 is inverted x 1 x x x igp0 at default polarity 0 xxxx igp0 is inverted 1 xxxx x-port signal definitions text slicer control bits d7 to d5 iswp1 iswp0 illv video data limited to range 1 to 254 x x 0 video data limited to range 8 to 247 x x 1 dword byte swap, in?uences serial output timing d0 d1 d2 d3 t ff 00 00 sav c b 0y0c r 0y1 00x d1 d0 d3 d2 t 00 ff sav 00 y0 c b 0y1c r 001x d2 d3 d0 d1 t 00savff00c r 0y1c b 0y0 1 0 x d3 d2 d1 d0 t sav0000ffy1c r 0y0c b 011x
2000 mar 15 114 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 89 i-port fifo ?ag control and arbitration; global set 86h[3:0] x = dont care. table 90 i-port fifo ?ag control and arbitration; global set 86h[7:4] x = dont care. i-port fifo flag control and arbitration control bits d3 to d0 ffl1 ffl0 fel1 fel0 fae fifo ?ag almost empty level <16 dwords x x 0 0 <8 dwords x x 0 1 <4 dwords x x 1 0 0 dwords x x 1 1 faf fifo ?ag almost full level 3 16 dwords 0 0 x x 3 24 dwords 0 1 x x 3 28 dwords 1 0 x x 32 dwords 1 1 x x function control bits d7 to d4 vitx1 vitx0 idg02 idg12 see subaddress 84h: idg11 and idg10 x x x 0 xxx1 see subaddress 84h: idg01 and idg00 x x 0 x xx1x i-port signal de?nitions i-port data output inhibited 0 0 x x only video data are transferred 0 1 x x only text data are transferred (no eav, sav will occur) 1 0 x x text and video data are transferred, text has priority 1 1 x x
2000 mar 15 115 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 91 i-port i/o enable, output clock and gated clock phase control; global set 87h[7:4] notes 1. x = dont care. 2. ipck3 and ipck2 only affects the gated clock (subaddress 80h, bit icks2 = 1). table 92 i-port i/o enable, output clock and gated clock phase control; global set 87h[1:0] 15.5.3 s ubaddress 88h table 93 power save control; global set 88h[3] and 88h[1:0] x = dont care. output clock and gated clock phase control control bits d7 to d4 (1) ipck3 (2) ipck2 (2) ipck1 ipck0 iclk default output phase x x 0 0 iclk phase shifted by 1 2 clock cycle t recommended for icks1 = 1 and icks0 = 0 (subaddress 80h) xx01 iclk phase shifted by about 3 ns x x 1 0 iclk phase shifted by 1 2 clock cycle + about 3 ns t alternatively to setting 01 x x 1 1 idq = gated clock default output phase 0 0 x x idq = gated clock phase shifted by 1 2 clock cycle t recommended for gated clock output 01xx idq = gated clock phase shifted by about 3 ns 1 0 x x idq = gated clock phase shifted by 1 2 clock cycle + about 3 ns t alternatively to setting 01 11xx i-port i/o enable control bits d1 and d0 ipe1 ipe0 i-port output is disabled by software 0 0 i-port output is enabled by software 0 1 i-port output is enabled by pin itri at logic 0 1 0 i-port output is enabled by pin itri at logic 1 1 1 power save control control bits 88h[3] 88h[1:0] slm3 slm1 slm0 decoder and vbi slicer are in operational mode x x 0 decoder and vbi slicer are in power-down mode; scaler only operates, if scaler input and iclk source is the x-port (refer to subaddresses 80h and 91h/c1h) xx1 scaler is in operational mode x 0 x scaler is in power-down mode; scaler in power-down stops i-port output x 1 x audio clock generation active 0 x x audio clock generation in power-down and output disabled 1 x x
2000 mar 15 116 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 94 power save control; global set 88h[7:4] notes 1. x = dont care. 2. bit swrst is now located here. 15.5.4 s ubaddress 8fh ( read - only register ) table 95 status information scaler part; 8fh[7:0] note 1. status information is unsynchronized and shows the actual status at the time of i 2 c-bus read. power save control control bits d7 to d4 (1) ch4en ch2en swrst (2) dprog dprog = 0 after reset x x x 0 dprog = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit prdon; if dprog was set to logic 1 and prdon status bit shows a logic 0 a power- or start-up fail has occurred xxx1 scaler path is reset to its idle state, software reset x x 0 x scaler is switched back to operation x x 1 x ad1x analog channel is in power-down mode x 0 x x ad1x analog channel is active x 1 x x ad2x analog channel is in power-down mode 0 x x x ad2x analog channel is active 1 x x x bit i2c-bus status bit function (1) d7 xtri status on input pin xtri, if not used for 3-state control, usable as hardware ?ag for software use d6 itri status on input pin itri, if not used for 3-state control, usable as hardware ?ag for software use d5 ffil status of the internal fifo almost ?lled ?ag d4 ffov status of the internal fifo over?ow ?ag d3 prdon copy of bit dprog, can be used to detect power-up and start-up fails d2 err_of error ?ag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate con?icts, e.g. if output data rate is much too low and all internal fifo capacity used d1 fidsci status of the ?eld sequence id at the scalers input d0 fidsco status of the ?eld sequence id at the scalers output, scaler processing dependent
2000 mar 15 117 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.5.5 s ubaddresses 90h and c0h table 96 task handling control; register set a (90h[2:0]) and b (c0h[2:0]) x = dont care. table 97 task handling control; register set a (90h[5:3]) and b (c0h[5:3]) table 98 task handling control; register set a (90h[7:6]) and b (c0h[7:6]) x = dont care. event handler control control bits d2 to d0 rptsk strc1 strc0 event handler triggers immediately after ?nishing a task x 0 0 event handler triggers with next v-sync x 0 1 event handler triggers with ?eld id = 0 x 1 0 event handler triggers with ?eld id = 1 x 1 1 if active task is ?nished, handling is taken over by the next task 0 x x active task is repeated once, before handling is taken over by the next task 1 x x event handler control control bits d5 to d3 fskp2 fskp1 fskp0 active task is carried out directly 0 0 0 1 ?eld is skipped before active task is carried out 0 0 1 ... ?elds are skipped before active task is carried out ... ... ... 6 ?elds are skipped before active task is carried out 1 1 0 7 ?elds are skipped before active task is carried out 1 1 1 event handler control control bits d7 and d6 conlh ofidc output ?eld id is ?eld id from scaler input x 0 output ?eld id is task status ?ag, which changes every time an selected task is activated (not synchronized to input ?eld id) x1 scaler sav/eav byte bit d7 and task ?ag = 1, default 0x scaler sav/eav byte bit d7 and task ?ag = 0 1 x
2000 mar 15 118 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.5.6 s ubaddresses 91h to 93h table 99 x-port formats and con?guration; register set a (91h[2:0]) and b (c1h[2:0]) notes 1. x = dont care. 2. fsc2 and fsc1 only to be used, if x-port input source dont provide chroma information for every input line. x-port input stream must contain dummy chroma bytes. table 100 x-port formats and con?guration; register set a (91h[7:3]) and b (c1h[7:3]) x = dont care. scaler input format and configuration format control control bits d2 to d0 (1) fsc2 (2) fsc1 (2) fsc0 input is yuv 4 : 2 : 2 like sampling scheme x x 0 input is yuv 4 : 1 : 1 like sampling scheme x x 1 chroma is provided every line, default 00x chroma is provided every 2nd line 0 1 x chroma is provided every 3rd line 1 0 x chroma is provided every 4th line 1 1 x scaler input format and configuration source selection control bits d7 to d3 conlv hldfv scsrc1 scsrc0 scrqe only if xrqt[83h[2]] = 1: scaler input source reacts on SAA7114h request xxxx0 scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1, if SAA7114h decoder part is source of scaler or xrqt[83h[2]] = 0) xxxx1 scaler input source is data from decoder, data type is provided according to table 14 xx0 0x scaler input source is yuv data from x-port x x 0 1 x scaler input source is raw digital cvbs from selected analog channel, for backward compatibility only, further use is not recommended xx1 0x scaler input source is raw digital cvbs (or 16-bit y + uv, if no 16-bit output are active) from x-port xx1 1x sav/eav code bits d6 and d5 (f and v) may change between sav and eav x0xxx sav/eav code bits d6 and d5 (f and v) are synchronized to scalers output line start x1xxx sav/eav code bit d5 (v) and v-gate on pin igpv as generated by the internal processing, see fig.36 0xxxx sav/eav code bit d5 (v) and v-gate are inverted 1 xxxx
2000 mar 15 119 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 101 x-port input reference signal de?nitions; register set a (92h[3:0]) and b (c2h[3:0]) x = dont care. table 102 x-port input reference signal de?nitions; register set a (92h[7:4]) and b (c2h[7:4]) x = dont care. x-port input reference signal definitions control bits d3 to d0 xcode xdh xdq xcks xclk input clock and xdq input quali?er are needed x x x 0 data rate is de?ned by xclk only, no xdq signal used x x x 1 data are quali?ed at xdq input at logic 1 x x 0 x data are quali?ed at xdq input at logic 0 x x 1 x rising edge of xrh input is horizontal reference x 0 x x falling edge of xrh input is horizontal reference x 1 x x reference signals are taken from xrh and xrv 0 x x x reference signals are decoded from eav and sav 1 x x x scaler input reference signal definitions control bits d7 to d4 xfdv xfdh xdv1 xdv0 rising edge of xrv input and decoder v123 is vertical reference x x x 0 falling edge of xrv input and decoder v123 is vertical reference x x x 1 xrv is a v-sync or v-gate signal x x 0 x xrv is a frame sync, v-pulses are generated internally on both edges of fs input xx1x x-port ?eld id is state of xrh at reference edge on xrv (de?ned by xfdv) x0xx field id (decoder and x-port ?eld id) is inverted x 1 x x reference edge for ?eld detection is falling edge of xrv 0 x x x reference edge for ?eld detection is rising edge of xrv 1 x x x
2000 mar 15 120 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 103 i-port output format and con?guration; register set a (93h[4:0]) and b (c3h[4:0]) x = dont care. table 104 i-port output format and con?guration; register set a (93h[7:5]) and b (c3h[7:5]) x = dont care. i-port output format and configuration control bits d4 to d0 foi1 foi0 fsi2 fsi1 fsi0 4:2:2 dw ord formatting x x 0 0 0 4:1:1 dw ord formatting x x 0 0 1 4:2:0, only every 2nd line y + uv output, in between y only output xx010 4:1:0, only every 4th line y + uv output, in between y only output xx011 y only x x 1 0 0 not de?ned x x 1 0 1 not de?ned x x 1 1 0 not de?ned x x 1 1 1 no leading y only line, before 1st y + uv line is output 0 0 x x x 1 leading y only line, before 1st y + uv line is output 0 1 x x x 2 leading y only lines, before 1st y + uv line is output 1 0 x x x 3 leading y only lines, before 1st y + uv line is output 1 1 x x x i-port output format and configuration control bits d7 to d5 icode i8_16 fysk all lines will be output x x 0 skip the number of leading y only lines, as de?ned by foi1 and foi0 x x 1 dwords are transferred byte wise, see subaddress 85h bits iswp1 and iswp0 x 0 x dwords are transferred 16-bit word wise via ipd and hpd, see subaddress 85h bits iswp1 and iswp0 x1x no itu 656 like sav/eav codes are available 0 x x itu 656 like sav/eav codes are inserted in the output data stream, framed by a quali?er 1xx
2000 mar 15 121 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.5.7 s ubaddresses 94h to 9bh table 105 horizontal input window start; register set a (94h[7:0]; 95h[3:0]) and b (c4h[7:0]; c5h[3:0]) note 1. reference for counting are luminance samples. table 106 horizontal input window length; register set a (96h[7:0]; 97h[3:0]) and b (c6h[7:0]; c7h[3:0]) note 1. reference for counting are luminance samples. table 107 vertical input window start; register set a (98h[7:0]; 99h[3:0]) and b (c8h[7:0]; c9h[3:0]) note 1. for trigger condition: strc[1:0]90h[1:0] = 00; yo + ys > (number of input lines per field - 2), will result in field dropping. other trigger conditions: yo > (number of input lines per field - 2), will result in field dropping. horizontal input acquisition window definition offset in x (horizontal) direction (1) control bits a(95h[3:0]) b(c5h[3:0]) a(94h[7:0]) b(c4h[7:0]) xo11 xo10 xo9 xo8 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 a minimum of 2 should be kept, due to a line counting mismatch 0 0 0000000010 odd offsets are changing the uv sequence in the output stream to vu sequence 0 0 0000000011 maximum possible pixel offset = 4095 1 1 1111111111 horizontal input acquisition window definition input window length in x (horizontal) direction (1) control bits a (97h[3:0]) b (c7h[3:0]) a(96h[7:0]) b(c6h[7:0]) xs11 xs10 xs9 xs8 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 no output 0 0 0000000000 odd lengths are allowed, but will be rounded up to even lengths 0 0 0000000001 maximum possible number of input pixels = 4095 1 1 1111111111 vertical input acquisition window definition offset in y (vertical) direction (1) control bits a(98h[3:0]) b(c8h[3:0]) a(98h[7:0]) b(c8h[7:0]) yo11 yo10 yo9 yo8 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 line offset = 0 0 0 0000000000 line offset = 1 0 0 0000000001 maximum line offset = 4095 1 1 1111111111
2000 mar 15 122 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 108 vertical input window length; register set a (9ah[7:0]; 9bh[3:0]) and b (cah[7:0]; cbh[3:0]) note 1. for trigger condition: strc[1:0]90h[1:0] = 00; yo + ys > (number of input lines per field - 2), will result in field dropping. other trigger conditions: ys > (number of input lines per field - 2), will result in field dropping. 15.5.8 s ubaddresses 9ch to 9fh table 109 horizontal output window length; register set a (9ch[7:0]; 9dh[3:0]) and b (cch[7:0]; cdh[3:0]) notes 1. reference for counting are luminance samples. 2. if the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. table 110 vertical output window length; register set a (9eh[7:0]; 9fh[3:0]) and b (ceh[7:0]; cfh[3:0]) note 1. if the desired output length is greater than the number of scaled output lines, the processing is cut. vertical input acquisition window definition input window length in y (vertical) direction (1) control bits a(9bh[3:0]) b(cbh[3:0]) a(9ah[7:0]) b(cah[7:0]) ys11 ys10 ys9 ys8 ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 no input lines 0 0 0 0 00000000 1 input line 0 0 0 0 00000001 maximum possible number of input lines = 4095 1 1 1111111111 horizontal output acquisition window definition number of desired output pixel in x (horizontal) direction (1) control bits a(9dh[3:0]) b(cdh[3:0]) a(9ch[7:0]) b(cch[7:0]) xd11 xd10 xd9 xd8 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 no output 0 0 0 0 00000000 odd lengths are allowed, but will be ?lled up to even lengths 0 0 0000000001 maximum possible number of input pixels = 4095; note 2 1 1 1111111111 vertical output acquisition window definition number of desired output lines in y (vertical) direction control bits a(9fh[3:0]) b(cfh[3:0]) a(9eh[7:0]) b(ceh[7:0]) yd11 yd10 yd9 yd8 yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 no output 0 0 0000000000 1pixel 0 0 0000000001 maximum possible number of output lines = 4095; note 1 1 1 1111111111
2000 mar 15 123 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.5.9 s ubaddresses a0h to a2h table 111 horizontal prescaling; register set a (a0h[5:0]) and b (d0h[5:0]) table 112 accumulation length; register set a (a1h[5:0]) and b (d1h[5:0]) table 113 prescaler dc gain and fir pre?lter control; register set a (a2h[3:0]) and b (d2h[3:0]) x = dont care. horizontal integer prescaling ratio (xpsc) control bits d5 to d0 xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 not allowed 000000 down-scale = 1 000001 down-scale = 1 2 000010 ... ... ... ... ... ... ... down-scale = 1 63 111111 horizontal prescaler accumulation sequence length (xacl) control bits d5 to d0 xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 accumulation length = 1 000000 accumulation length = 2 000001 ... ... ... ... ... ... ... accumulation length = 64 111111 prescaler dc gain control bits d3 to d0 xc2_1 xdcg2 xdcg1 xdcg0 prescaler output is renormalized by gain factor = 1 x 0 0 0 prescaler output is renormalized by gain factor = 1 2 x001 prescaler output is renormalized by gain factor = 1 4 x010 prescaler output is renormalized by gain factor = 1 8 x011 prescaler output is renormalized by gain factor = 1 16 x100 prescaler output is renormalized by gain factor = 1 32 x101 prescaler output is renormalized by gain factor = 1 64 x110 prescaler output is renormalized by gain factor = 1 128 x111 weighting of all accumulated samples is factor 1; e.g. xacl = 4 t sequence 1 + 1+1+1+1 0xxx weighting of samples inside sequence is factor 2; e.g. xacl = 4 t sequence 1 + 2+2+2+1 1xxx
2000 mar 15 124 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 114 prescaler dc gain and fir pre?lter control; register set a (a2h[7:4]) and b (d2h[7:4]) x = dont care. 15.5.10 s ubaddresses a4h to a6h table 115 luminance brightness setting; register set a (a4h[7:0]) and b (d4h[7:0]) table 116 luminance contrast setting; register set a (a5h[7:0]) and b (d5h[7:0]) table 117 chrominance saturation setting; register set a (a6h[7:0]) and b (d6h[7:0]) fir prefilter control control bits d7 to d4 pfuv1 pfuv0 pfy1 pfy0 luminance fir ?lter bypassed x x 0 0 h_y(z) = 1 4 (1 2 1) x x 0 1 h_y(z) = 1 8 ( - 1 1 1.75 4.5 1.75 1 - 1) x x 1 0 h_y(z) = 1 8 (12221) x x 1 1 chrominance fir ?lter bypassed 0 0 x x h_uv(z) = 1 4 (1 2 1) 0 1 x x h_uv(z) = 1 32 (381083) 1 0 x x h_uv(z) = 1 8 (1 2 2 2 1) 1 1 x x luminance brightness setting control bits d7 to d0 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 value = 0 00000000 nominal value = 128 10000000 value = 255 11111111 luminance contrast setting control bits d7 to d0 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 gain = 0 00000000 gain = 1 64 00000001 nominal gain = 64 01000000 gain = 127 64 01111111 chrominance saturation setting control bits d7 to d0 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 gain = 0 00000000 gain = 1 64 00000001 nominal gain = 64 01000000 gain = 127 64 01111111
2000 mar 15 125 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.5.11 s ubaddresses a8h to aeh table 118 horizontal luminance scaling increment; register set a (a8h[7:0]; a9h[7:0]) and b (d8h[7:0]; d9h[7:0]) table 119 horizontal luminance phase offset; register set a (aah[7:0]) and b (dah[7:0]) table 120 horizontal chrominance scaling increment; register set a (ach[7:0]; adh[7:0]) and b (dch[7:0]; ddh[7:0]) note 1. bits xscc[15:13] are reserved and are set to logic 0. table 121 horizontal chrominance phase offset; register set a (aeh[7:0]) and b (deh[7:0]) horizontal luminance scaling increment control bits a(a9h[7:4]) b(d9h[7:4]) a(a9h[3:0]) b(d9h[3:0]) a(a8h[7:4]) b(d8h[7:4]) a(a8h[3:0]) b(d8h[3:0]) xscy[15:12] xscy[11:8] xscy[7:4] xscy[3:0] scale = 1024 1 (theoretical) zoom 0000 0000 0000 0000 scale = 1024 294 , lower limit de?ned by data path structure 0000 0001 0010 0110 scale = 1024 1023 zoom 0000 0011 1111 1111 scale = 1, equals 1024 0000 0100 0000 0000 scale = 1024 1025 down-scale 0000 0100 0000 0001 scale = 1024 8191 down-scale 0001 1111 1111 1111 horizontal luminance phase offset control bits d7 to d0 xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 offset = 0 0 0 000000 offset = 1 32 pixel 00000001 offset = 32 32 =1pixel 00100000 offset = 255 32 pixel 11111111 horizontal chrominance scaling increment control bits a (adh[7:4]) b (ddh[7:4]) a (adh[3:0]) b (ddh[3:0]) a (ach[7:4]) b (dch[7:4]) a (ach[3:0]) b (dch[3:0]) xscc[15:12] (1) xscc[11:8] xscc[7:4] xscc[3:0] this value must be set to the luminance value 1 2 xscy[15:0] 0000 0000 0000 0000 0000 0000 0000 0001 0001 1111 1111 1111 horizontal chrominance phase offset control bits d7 to d0 xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 this value must be set to 1 2 xphy[7:0] 0 0 000000 00000001 11111111
2000 mar 15 126 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 15.5.12 s ubaddresses b0h to bfh table 122 vertical luminance scaling increment; register set a (b0h[7:0]; b1h[7:0]) and b (e0h[7:0]; e1h[7:0]) table 123 vertical chrominance scaling increment; register set a (b2h[7:0]; b3h[7:0]) and b (e2h[7:0]; e3h[7:0]) table 124 vertical scaling mode control; register set a (b4h[4 and 0]) and b (e4h[4 and 0]) x = dont care. table 125 vertical chrominance phase offset 00; register set a (b8h[7:0]) and b (e8h[7:0]) vertical luminance scaling increment control bits a (b1h[7:4]) b (e1h[7:4]) a (b1h[3:0]) b (e1h[3:0]) a (b0h[7:4]) b (e0h[7:4]) a (b0h[3:0]) b (e0h[3:0]) yscy[15:12] yscy[11:8] yscy[7:4] yscy[3:0] scale = 1024 1 (theoretical) zoom 0000 0000 0000 0001 scale = 1024 1023 zoom 0000 0011 1111 1111 scale = 1, equals 1024 0000 0100 0000 0000 scale = 1024 1025 down-scale 0000 0100 0000 0001 scale = 1 63.999 down-scale 1111 1111 1111 1111 vertical chrominance scaling increment control bits a (b3h[7:4]) b (e3h[7:4]) a (b3h[3:0]) b (e3h[3:0]) a (b2h[7:4]) b (e2h[7:4]) a (b2h[3:0]) b (e2h[3:0]) yscc[15:12] yscc[11:8] yscc[7:4] yscc[3:0] this value must be set to the luminance value yscy[15:0] 0000 0000 0000 0001 1111 1111 1111 1111 vertical scaling mode control control bits d4 and d0 ymir ymode vertical scaling performs linear interpolation between lines x 0 vertical scaling performs higher order accumulating interpolation, better alias suppression x1 no mirroring 0x lines are mirrored 1 x vertical chrominance phase offset control bits d7 to d0 ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 offset = 0 0 0 000000 offset = 32 32 = 1 line 0 0 100000 offset = 255 32 lines 1 1 111111
2000 mar 15 127 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 126 vertical luminance phase offset 00; register set a (bch[7:0]) and b (ech[7:0]) 16 programming start set-up 16.1 decoder part the given values force the following behaviour of the SAA7114h decoder part: the analog input ai11 expects an ntsc m, pal bdghi or secam signal in cvbs format; analog anti-alias filter and agc active automatic field detection enabled standard itu 656 output format enabled on expansion (x) port contrast, brightness and saturation control in accordance with itu standards adaptive comb filter for luminance and chrominance activated pins llc, llc2, xtout, rts0, rts1 and rtco are set to 3-state. table 127 decoder part start set-up values for the three main standards vertical luminance phase offset control bits d7 to d0 ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 offset = 0 0 0 000000 offset = 32 32 = 1 line 0 0 100000 offset = 255 32 lines 1 1 111111 sub address (hex) register function bit name (1) values (hex) ntsc m pal bdghi secam 00 chip version id07 to id04 read only 01 horizontal increment delay x, x, x, x, idel3 to idel0 08 08 08 02 analog input control 1 fuse1 and fuse0, gudl1 to gudl0, mode3 to mode0 c0 c0 c0 03 analog input control 2 x, hlnrs, vbsl, wpoff, holdg, gafix, gai28 and gai18 10 10 10 04 analog input control 3 gai17 to gai10 90 90 90 05 analog input control 4 gai27 to gai20 90 90 90 06 horizontal sync start hsb7 to hsb0 eb eb eb 07 horizontal sync stop hss7 to hss0 e0 e0 e0 08 sync control aufd, fsel, foet, htc1, htc0, hpll, vnoi1 and vnoi0 98 98 98 09 luminance control byps, ycomb, ldel, lubw, lufi3 to lufi0 40 40 1b 0a luminance brightness control dbri7 to dbri0 80 80 80 0b luminance contrast control dcon7 to dcon0 44 44 44 0c chrominance saturation control dsat7 to dsat0 40 40 40
2000 mar 15 128 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h note 1. all x values must be set to low. 0d chrominance hue control huec7 to huec0 00 00 00 0e chrominance control 1 cdto, cstd2 to cstd0, dcvf, fctc, x, ccomb 89 81 d0 0f chrominance gain control acgc, cgain6 to cgain0 2a 2a 80 10 chrominance control 2 offu1, offu0, offv1, offv0, chbw, lcbw2 to lcbw0 0e 06 00 11 mode/delay control colo, rtp1, hdel1, hdel0, rtp0, ydel2 to ydel0 00 00 00 12 rt signal control rtse13 to rtse10, rtse03 to rtse00 00 00 00 13 rt/x-port output control rtce, xrhs, xrvs1, xrvs0, hlsel, ofts2 to ofts0 00 00 00 14 analog, adc, compatibility control cm99, uptcv, aosl1, aosl0, xtoute, oldsb, apck1 and apck0 00 00 00 15 vgate start, fid change vsta7 to vsta0 11 11 11 16 vgate stop vsto7 to vsto0 fe fe fe 17 miscellaneous/vgate msbs llce, llc2e, x, x, x, vgps, vsto8 and vsta8 40 40 40 18 raw data gain rawg7 to rawg0 40 40 40 19 raw data offset rawo7 to rawo0 80 80 80 1a to 1e reserved x, x, x, x, x, x, x, x 00 00 00 1f decoder status byte (oldsb = 0) intl, hvln, fidt, glimt, glimb, wipa, copro, rdcap read only sub address (hex) register function bit name (1) values (hex) ntsc m pal bdghi secam
2000 mar 15 129 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 16.2 audio clock generation part the given values force the following behaviour of the SAA7114h audio clock generation part: used crystal is 24.576 mhz expected field frequency is 59.94 hz (e.g. ntsc m standard) generated audio master clock frequency at pin amclk is 256 44.1 khz = 11.2896 mhz amclk is externally connected to amxclk (short-cut between pins 37 and 41) asclk = 32 44.1 khz = 1.4112 mhz alrclk is 44.1 khz. table 128 audio clock part set-up values note 1. all x values must be set to low. sub address (hex) register function bit name (1) start values 76543210hex 30 audio master clock cycles per ?eld; bits 7 to 0 acpf7 to acpf0 10111100 bc 31 audio master clock cycles per ?eld; bits 15 to 8 acpf15 to acpf8 11011111 df 32 audio master clock cycles per ?eld; bits 17 and 16 x, x, x, x, x, x, acpf17 and acpf16 00000010 02 33 reserved x, x, x, x, x, x, x, x 00000000 00 34 audio master clock nominal increment; bits 7 to 0 acni7 to acni0 11001101 cd 35 audio master clock nominal increment; bits 15 to 8 acni15 to acni8 11001100 cc 36 audio master clock nominal increment; bits 21 to 16 x, x, acni21 to acni16 00111010 3a 37 reserved x, x, x, x, x, x, x, x 00000000 00 38 clock ratio amxclk to asclk x, x, sdiv5 to sdiv0 00000011 03 39 clock ratio asclk to alrclk x, x, lrdiv5 to lrdiv0 00010000 10 3a audio clock generator basic set-up x, x, x, x, apll, amvr, lrph, scph 00000000 00 3b to 3f reserved x, x, x, x, x, x, x, x 00000000 00
2000 mar 15 130 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 16.3 data slicer and data type control part the given values force the following behaviour of the SAA7114h vbi-data slicer part: closed captioning data are expected at line 21 of field 1 (60 hz/525 line system) all other lines are processed as active video sliced data are framed by itu 656 like sav/eav sequence (did[5:0] = 3eh t msb of sav/eav = 1). table 129 data slicer start set-up values notes 1. all x values must be set to low. 2. changes for 50 hz/625 line systems: subaddress 5ah = 03h and subaddress 5bh = 03h. sub address (hex) function bit name (1) start values 76543210hex 40 slicer control 1 x, ham_n, fce, hunt_n, x, x, x, x 0 1 0 00000 00 41 to 53 line control register 2 to 20 lcrn_7 to lcrn_0 (n = 2 to 20) 1 1 1 11111 ff 54 line control register 21 lcr21_7 to lcr21_0 0 1 0 11111 5f 55 to 57 line control register 22 to 24 lcrn_7 to lcrn_0 (n = 22 to 24) 1 1 1 11111 ff 58 programmable framing code fc7 to fc0 0 0 0 00000 00 59 horizontal offset for slicer hoff7 to hoff0 0 1 0 00111 47 5a vertical offset for slicer voff7 to voff0 0 0 0 0011006 (2) 5b ?eld offset and msbs for horizontal and vertical offset foff, recode, x, voff8, x, hoff10 to hoff8 1000001183 (2) 5c reserved x, x, x, x, x, x, x, x 0 0 0 00000 00 5d header and data identi?cation code control fvref, x, did5 to did0 0 0 1 11110 3e 5e sliced data identi?cation code x, x, sdid5 to sdid0 0 0 0 00000 00 5f reserved x, x, x, x, x, x, x, x 0 0 0 00000 00 60 slicer status byte 1 - , fc8v, fc7v, vpsv, ppv, ccv, - , - read-only register 61 slicer status byte 2 - , - , f21_n, ln8 to ln4 read-only register 62 ln3 to ln0, dt3 to dt0 read-only register
2000 mar 15 131 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 16.4 scaler and interfaces table 130 shows some examples for the scaler programming with: prsc = prescale ratio fisc = fine scale ratio vsc = vertical scale ratio. the ratio is defined as: in the following settings the vbi-data slicer is inactive. to activate the vbi-data slicer, vitx[1:0]86h[7:6] has to be set to 11. dependent on the vbi-data slicer settings, the sliced vbi-data are inserted after end of scaled video lines, if the regions of vbi-data slicer and scaler overlaps. to compensate the running-in of the vertical scaler, the vertical input window lengths are extended by 2 to 290 lines, respectively 242 lines for xs, but the scaler increment calculations are done with 288, respectively 240 lines. 16.4.1 t rigger condition for trigger condition strc[1:0]90h[1:0] not equal 00. if the value of (yo + ys) is greater equal 262 (ntsc), respectively 312 (pal) the output field rate is reduced to 30 hz, respectively 25 hz. horizontal and vertical offsets (xo and yo) have to be used to adjust the displayed video in the display window. as this adjustment is application dependent, the listed values are only dummy values. 16.4.2 m aximum zoom factor the maximum zoom factor is dependent on the back-end data rate and therefore back-end clock and data format dependent (8 or 16-bit output). the maximum horizontal zoom is limited to about 3.5, due to internal data path restrictions. number of input pixel number of output pixel ---------------------------------------------------------- - 16.4.3 e xamples table 130 example con?gurations example number scaler source and reference events input window output window scale ratios 1 analog input to 8-bit i-port output, with sav/eav codes, 8-bit serial byte stream decoder output at x-port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; h and v-gates on igph and igpv, igp0 = vbi sliced data ?ag, igp1 = fifo almost full, level 3 24, idq quali?er logic 1 active 720 240 720 240 prsc = 1; ?sc = 1; vsc = 1 2 analog input to 16-bit output, without sav/eav codes, y on i-port, uv on h-port and decoder output at x-port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; h and v-pulses on igph and igpv, output fid on igp0, igp1 ?xed to logic 1, idq quali?er logic 0 active 704 288 768 288 prsc = 1; ?sc = 0.91667; vsc = 1 3 x-port input 8 bit with sav/eav codes, no reference signals on xrh and xrv, xclk as gated clock; ?eld detection and acquisition trigger on different events; acquisition triggers at rising edge vertical and rising edge horizontal; i-port output 8 bit with sav/eav codes like example number 1 720 240 352 288 prsc = 2; ?sc = 1.022; vsc = 0.8333 4 x-port and h-port for 16-bit yuv 4 : 2 : 2 input (if no 16-bit output selected); xrh and xrv as references; ?eld detection and acquisition trigger at falling edge vertical and rising edge horizontal; i-port output 8 bit with sav/eav codes, but y only output 720 288 200 80 prsc = 2; ?sc = 1.8; vsc = 3.6
2000 mar 15 132 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h table 131 scaler and interface con?guration example i 2 c-bus address (hex) main functionality example 1 example 2 example 3 example 4 hex dec hex dec hex dec hex dec global settings 80 task enable, idq and back-end clock de?nition 10 - 10 - 10 - 10 - 83 xclk output phase and x-port output enable 01 - 01 - 00 - 00 - 84 igph, igpv, igp0 and igp1 output de?nition a0 - c5 - a0 - a0 - 85 signal polarity control and i-port byte swapping 10 - 09 - 10 - 10 - 86 fifo ?ag thresholds and video/text arbitration 45 - 40 - 45 - 45 - 87 iclk and idq output phase and i-port enable 01 - 01 - 01 - 01 - 88 power save control and software reset f0 - f0 - f0 - f0 - task a: scaler input con?guration and output format settings 90 task handling 00 - 00 - 00 - 00 - 91 scaler input source and format de?nition 08 - 08 - 18 - 38 - 92 reference signal de?nition at scaler input 10 - 10 - 10 - 10 - 93 i-port output formats and con?guration 80 - 40 - 80 - 84 - input and output window de?nition 94 horizontal input offset (xo) 10 16 10 16 10 16 10 16 95 00 - 00 - 00 - 00 - 96 horizontal input (source) window length (xs) d0 720 c0 704 d0 720 d0 720 97 02 - 02 - 02 - 02 - 98 vertical input offset (yo) 0a 10 0a 10 0a 10 0a 10 99 00 - 00 - 00 - 00 - 9a vertical input (source) window length (ys) f2 242 22 290 f2 242 22 290 9b 00 - 01 - 00 - 01 - 9c horizontal output (destination) window length (xd) d0 720 00 768 60 352 c8 200 9d 02 - 03 - 01 - 00 - 9e vertical output (destination) window length (yd) f0 240 20 288 20 288 50 80 9f 00 - 01 - 01 - 00 - pre?ltering and prescaling a0 integer prescale (value 00 not allowed) 01 - 01 - 02 - 02 - a1 accumulation length for prescaler 00 - 00 - 02 - 03 - a2 fir pre?lter and prescaler dc normalization 00 - 00 - aa - f2 - a4 scaler brightness control 80 128 80 128 80 128 80 128 a5 scaler contrast control 40 64 40 64 40 64 11 17 a6 scaler saturation control 40 64 40 64 40 64 11 17
2000 mar 15 133 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h horizontal phase scaling a8 horizontal scaling increment for luminance 00 1024 aa 938 18 1048 34 1844 a9 04 - 03 - 04 - 07 - aa horizontal phase offset luminance 00 - 00 - 00 - 00 - ac horizontal scaling increment for chrominance 00 512 d5 469 0c 524 9a 922 ad 02 - 01 - 02 - 03 - ae horizontal phase offset chrominance 00 - 00 - 00 - 00 - vertical scaling b0 vertical scaling increment for luminance 00 1024 00 1024 55 853 66 3686 b1 04 - 04 - 03 - 0e - b2 vertical scaling increment for chrominance 00 1024 00 1024 55 853 66 3686 b3 04 - 04 - 03 - 0e - b4 vertical scaling mode control 00 - 00 - 00 - 01 - b8 to bf vertical phase offsets luminance and chrominance (need to be used for interlace correct scaled output) start with b8 to bf at 00h, if there are no problems with the interlaced scaled output optimize according to section 8.3.3.2 i 2 c-bus address (hex) main functionality example 1 example 2 example 3 example 4 hex dec hex dec hex dec hex dec
2000 mar 15 134 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 17 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-01-19 00-02-01 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
2000 mar 15 135 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 18 soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 18.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 mar 15 136 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 18.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 mar 15 137 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h 19 definitions 20 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 21 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2000 mar 15 138 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h notes
2000 mar 15 139 philips semiconductors preliminary speci?cation pal/ntsc/secam video decoder with adaptive pal/ntsc comb ?lter, vbi-data slicer and high performance scaler SAA7114h notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753505/01/pp 140 date of release: 2000 mar 15 document order number: 9397 750 05976

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